ELEVATOR AILERON COMPUTER SYSTEM (ELAC) - DESCRIPTION AND OPERATION

** ON A/C NOT FOR ALL

1. General
The ELAC (Elevator and Aileron Computer) is in charge of the control of the elevators and ailerons and of the THS positioning.
Each aircraft has two ELACs.
Each computer has two units:

The COM unit which mainly calculates the deflection orders as a function of the received signals and slaves the control surfaces.
The MON unit which mainly checks that the orders are correctly executed.

** ON A/C NOT FOR ALL

2. Component Location

ELAC Location

FIN	FUNCTIONAL DESIGNATION	PANEL	ZONE	ATA REF
** ON A/C ALL
2CE1	ELAC-1	83VU	127	27-93-34
2CE2	ELAC-2	84VU	128	27-93-34

** ON A/C NOT FOR ALL

3. Power Supply
The ELAC 1 is supplied from a DC essential busbar 4PP, the battery 1 taking overinstantaneously through a dedicated diode device (Power Supply Decoupling Unit) when the voltage level drops below the battery output voltage. A relay ensures the battery supply line breaking on the ground 30s after the second engine shut down.

ELAC 1 Power Supply (Principle)

The ELAC 2 is normally supplied from the normal busbar 2PP. In case of loss of this busbar (particularly after the loss of both main generation channels, or after a double main TRU failure), this supply is automatically switched over to the battery 2 by means of two relays, for a fixed period of 30s.

ELAC 2 Power Supply (Principle) ** ON A/C NOT FOR ALL

These relays are automatically re-energized if later on the blue hydraulic pressure falls and during the landing phase as soon as the nose landing gear is extended.

** ON A/C NOT FOR ALL

4. Component Description

A. General FIN: 2-CE-1 FIN: 2-CE-2
The ELAC is in the form of a case to ARINC 600 standard.
There are 10 electronic boards which are plugged in from the front of the unit when opened.
The COM unit (5 boards) and MON unit (5 boards) are separated by a center partition.
Each unit has its own power supply board located close to the longitudinal mid plane.
The 10 electronic boards are as follows:

ELAC - Location of Boards

MON unit:
. MAN: Monitor Analog board
. MPU: Monitor Processing board
. MDG: Monitor Digital board
. MSP: Monitor Slave Processing board
. MPS: Monitor Power Supply
COM unit:
. CPS: Command Power Supply
. CDG: Command Digital board
. CPU: Command Processing board
. CAN: Command Analog board
. CSP: Command Slave Processing board

(1) Leading Particulars
The main characteristics are summarized in the table below:

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I ELECTRICAL CHARACTERISTICS I

I-----------------------------------------------------------------------------I

I POWER SUPPLY I 28 VDC I

I CONSUMPTION I < 100 W I

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I I N P U T S I

I-----------------------------------------------------------------------------I

I ANALOG I ANI 1 : 4 (COM), 4 (MON) I SIDE STICKS I

I I ANI 2 : 6 (COM), 6 (MON) I SURFACE POS. TRANSDUCER I

I I ANI 3 : 0 (COM), 2 (MON) I SV SELECTOR VALVE TRANSDUCER I

I I ANI 4 : 6 (COM), 6 (MON) I ACCELEROMETERS, PRESSURE TRANSMITTERSI

I I ANI 7 : 0 (COM), 4 (MON) I SOL V SELECTOR VALVE TRANSDUCER I

I I I I

I DIGITAL I DGI 1 (HIGH SPEED) I ASSOCIATED UNIT I

I I DGI 2 (HIGH SPEED) I ADIRS (IRS) I

I I DGI 3 (HIGH SPEED) I ADIRS (IRS) I

I I DGI 4 (LOW SPEED) I FMGC 1 I

I I DGI 5 (LOW SPEED) I FMGC 2 I

I I DGI 6 (LOW SPEED) I ADIRS (IRS) I

I I DGI 7 (LOW SPEED) I ADIRS (IRS) I

I I DGI 8 (LOW SPEED) I TESTS I

I I DGI 9 (LOW SPEED) I ASSOCIATED UNIT I

I I DGI 10 (LOW SPEED) I RADIO ALTIMETER I

I I DGI 11 (LOW SPEED) I SFCC I

I I DGI 12 (LOW SPEED) I FCDC I

I I DGI 13 (LOW SPEED) I SPARE I

I I DGI 14 (LOW SPEED) I SEC I

I I DGI 15 (LOW SPEED) I OTHER ELAC I

I I I

I DISCRETE I 56 (COM), 56 (MON) I

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I O U T P U T S I

I-----------------------------------------------------------------------------I

I 5 ANALOG I ANO 1 I L ELEVATOR SERVO VALVE CURRENT I

I(COM only)I ANO 2 I R ELEVATOR SERVO VALVE CURRENT I

I I ANO 3 I THS MOTOR CURRENT I

I I ANO 4 I R AILERON SERVO VALVE CURRENT I

I I ANO 5 I L AILERON SERVO VALVE CURRENT I

I I I I

I DIGITAL I DGO 1 I TO SEC, FAC and BSCU I

I I DGO 2 I FCDC I

I I DGO 3 I SPARE I

I I DGO 4 I ASSOCIATED UNIT I

I I DGO 5 I OPPOSITE ELAC I

I I I

I DISCRETE I 14 (COM), 14 (MON) I

I I I

I RELAY I 13 (COM), 13 (MON) I

------------------------------------------------------------------------------I

(2) Leading Particulars
The main characteristics are summarized in the table below:

-------------------------------------------------------------------------------

I ELECTRICAL CHARACTERISTICS I

I-----------------------------------------------------------------------------I

I POWER SUPPLY I 28 VDC I

I CONSUMPTION I < 100 W I

-------------------------------------------------------------------------------

I I N P U T S I

I-----------------------------------------------------------------------------I

I ANALOG I ANI 1 : 4 (COM), 4 (MON) I SIDE STICKS I

I I ANI 2 : 6 (COM), 6 (MON) I SURFACE POS. TRANSDUCER I

I I ANI 3 : 0 (COM), 2 (MON) I SV SELECTOR VALVE TRANSDUCER I

I I ANI 4 : 6 (COM), 6 (MON) I ACCELEROMETERS, PRESSURE TRANSMITTERSI

I I ANI 7 : 0 (COM), 4 (MON) I SOL V SELECTOR VALVE TRANSDUCER I

I I I I

I DIGITAL I DGI 1 (HIGH SPEED) I ASSOCIATED UNIT I

I I DGI 2 (HIGH SPEED) I ADIRS (IRS) I

I I DGI 3 (HIGH SPEED) I ADIRS (IRS) I

I I DGI 4 (LOW SPEED) I FMGC 1 I

I I DGI 5 (LOW SPEED) I FMGC 2 I

I I DGI 6 (LOW SPEED) I ADIRS (IRS) I

I I DGI 7 (LOW SPEED) I ADIRS (IRS) I

I I DGI 8 (LOW SPEED) I TESTS I

I I DGI 9 (LOW SPEED) I ASSOCIATED UNIT I

I I DGI 10 (LOW SPEED) I RADIO ALTIMETER I

I I DGI 11 (LOW SPEED) I SFCC I

I I DGI 12 (LOW SPEED) I FCDC I

I I DGI 13 (LOW SPEED) I MDDU TO ELAC I

I I DGI 14 (LOW SPEED) I SEC I

I I DGI 15 (LOW SPEED) I OTHER ELAC I

I I I

I DISCRETE I 56 (COM), 56 (MON) I

-------------------------------------------------------------------------------

I O U T P U T S I

I-----------------------------------------------------------------------------I

I 5 ANALOG I ANO 1 I L ELEVATOR SERVO VALVE CURRENT I

I(COM only)I ANO 2 I R ELEVATOR SERVO VALVE CURRENT I

I I ANO 3 I THS MOTOR CURRENT I

I I ANO 4 I R AILERON SERVO VALVE CURRENT I

I I ANO 5 I L AILERON SERVO VALVE CURRENT I

I I I I

I DIGITAL I DGO 1 I TO SEC, FAC and BSCU I

I I DGO 2 I FCDC I

I I DGO 3 I ELAC TO MDDU I

I I DGO 4 I ASSOCIATED UNIT I

I I DGO 5 I OPPOSITE ELAC I

I I I

I DISCRETE I 14 (COM), 14 (MON) I

I I I

I RELAY I 13 (COM), 13 (MON) I

------------------------------------------------------------------------------I

(3) Discrete outputs

ELAC1

-------------------------------------------------------------------------------

NAME ELECTRICAL LEVEL TO SIGNAL STATUS

-------------------------------------------------------------------------------

L AIL OK COM GND/O C ELAC1 MON GND=OK

ELAC2 COM

L AIL OK MON GND/O C ELAC1 COM GND=OK

ELAC2 MON

R AIL OK COM GND/O C ELAC1 MON GND=OK

ELAC2 COM

R AIL OK COM GND/O C ELAC1 COM GND=OK

ELAC2 MON

DGTL O/P VALIDATED COM GND/O C ELAC1 MON GND=VALIDATED

SEC2 COM

SEC2 MON

SEC3 COM

SEC3 MON

FAC2

BSCU

DGTL O/P VALIDATED MON GND/O C ELAC1 COM GND=VALIDATED

SEC1 COM

SEC1 MON

FAC1

BSCU

AP1 AUTHORIZED COM GND/O C FMGC1 GND=AUTHORIZED

AP1 AUTHORIZED MON GND/O C FMGC1 GND=AUTHORIZED

AP2 AUTHORIZED COM GND/O C FMGC2 GND=AUTHORIZED

AP2 AUTHORIZED MON GND/O C FMGC2 GND=AUTHORIZED

PITCH AXIS OK COM GND/O C ELAC1 MON GND=OK

SEC1 COM

SEC1 MON

SEC2 COM

SEC2 MON

PITCH AXIS OK MON GND/O C ELAC1 COM GND=OK

SEC1 COM

SEC1 MON

SEC2 COM

SEC2 MON

ELAC2

-------------------------------------------------------------------------------

NAME ELECTRICAL LEVEL TO SIGNAL STATUS

-------------------------------------------------------------------------------

PITCH AXIS OK COM GND/O C ELAC2 MON GND=OK

ELAC1 COM

ELAC1 MON

PITCH AXIS OK MON GND/O C ELAC2 COM GND=OK

ELAC1 COM

ELAC1 MON

DGTL O/P VALIDATED COM GND/O C ELAC2 MON GND=VALIDATED

SEC1 COM

SEC1 MON

FAC1

BSCU

DGTL O/P VALIDATED MON GND/O C ELAC2 COM GND=VALIDATED

SEC2 COM

SEC2 MON

SEC3 COM

SEC3 MON

FAC2

BSCU

AP1 AUTHORIZED COM GND/O C FMGC1 GND=AUTHORIZED

AP1 AUTHORIZED MON GND/O C FMGC1 GND=AUTHORIZED

AP2 AUTHORIZED COM GND/O C FMGC2 GND=AUTHORIZED

AP2 AUTHORIZED MON GND/O C FMGC2 GND=AUTHORIZED

PITCH AXIS OK COM GND/O C ELAC2 MON GND=OK

SEC1 COM

SEC1 MON

SEC2 COM

SEC2 MON

PITCH AXIS OK MON GND/O C ELAC2 COM GND=OK

SEC1 COM

SEC1 MON

SEC2 COM

SEC2 MON

(4) Protections
All the inputs and outputs are protected against spurious undervoltages by clipper circuits.
A 75 ohms resistor ensures the protection against the spurious application of 28VDC or 115VAC. This resistor acts as a fuse at each input and output, except on relay contacts.
All the analog and discrete inputs are filtered.

(5) Power supply of position transducers.
Each COM and MON unit supplies the position transducers that it uses:

+10VDC power for side stick transducers (ANI 1)
7VAC 1953 Hz power for inductive transducers (ANI 2, ANI 3, ANI 7).

(6) Computer architecture

ELAC Architecture

Each unit (COM or MON) has the functions below:

acquisition of digital inputs
generation of digital outputs
main processor
acquisition of discrete inputs
acquisition of analog inputs
generation of analog outputs (COM only)
generation of discrete outputs
control of switching relays.

The acquisition of digital inputs and the generation of digital outputs are performed by specific interfaces and by a specialized processor located on the CDG and MDG boards.
The main processor (CPU and MPU boards) executes the servoloop functions and calculates the laws.
It supplies the data required for the calculation of the laws and of the logic to the slave processor (slave processing board, CSP and MSP boards).
It communicates with the specialized processor of the digital input/ ouptut boards via a buffer memory.
The main processor directly manages the acquisition of the discrete inputs.
The other functions are:

acquisition of analog inputs and generation of analog outputs (CAN and MAN boards)
generation of discrete outputs and control of switching relays (MSP and CPS boards).

The slave processor (CSP and MSP boards) computes the laws and the logic.
It communicates with the main processor through a buffer memory.
The data transmission between boards is made through the bus located at the bottom part of the casing. This bus is under the exclusive control of the main processor.
The main processor directly controls the relay outputs. However, the specialized processor of the digital acquisition board can de-activate these relays or discrete outputs through a separate control.
The power supplies generated independently in each unit are distributed at the bottom of the casing to the other boards of the unit.
The control and monitoring channels exchange data through ARINC 429 and discrete links outside the casing.

B. Description of Boards

(1) CPU - MPU boards
These boards are identical and integrate the unit main processor.
They also include the interfaces with the discrete inputs.
Several components are shown

COM Unit Architecture

MON Unit Architecture

the 16-bit microprocessor of the 68000 family,
the clock and bus management circuitry,
the circuits required for microprocessor start and restart,
the read-write memory of the SRAM type (4 Kbytes),
the interrupt management circuits for the microprocessor,
the interface with the bus,
the real-time clock,
the watchdogs,
the non-volatile memory (NVRAM).

The purpose of this memory is to save the data related to the failures detected during operation if a power supply cutoff occurs.
This memory can be used in maintenance (BITE) (for shop maintenance only).
The saving or recall of data is made upon software command.
Discrete inputs
The discrete input interfaces receive:

40 GROUND-OPEN inputs
8 28VDC-OPEN inputs
8 reconfigurable inputs

The interfaces ensure the translation of the input levels into TTL-compatible levels (0-5V).
These 56 inputs are then multiplexed so as to make four 16-bit words that can be accessed by the microprocessor software.

(2) CAN-MAN boards
These boards manage the analog inputs from the various aircraft transducers. In particular, they ensure the analog/digital conversion of these data.
The MAN (in MON) and CAN (in COM) boards are of identical constitution for certain inputs.
The main differences are:

The MAN board processe additional inputs for the monitoring of servocontrols
COM Unit Architecture
The CAN board performs the digital/analog conversion of the servovalve control outputs
MON Unit Architecture
These boards ensure the functions below:
processing of inputs
multiplexing of DC voltages and analog/digital conversion
generation of DC and AC references for the board
DC and AC power supply of the transducers (+10VDC and 7V, 1953 Hz)
interface with the microprocessor bus and check of the board functions
protections against the application of a spurious overvoltage (lightning strike etc.).

(a) ANI 1 inputs - side stick transducers (CAN and MAN boards)
Schematic of interface for one channel

ANI 1 Input Interface

The two input amplifiers are wired as followers.
The SURV ouptut permits to detect the cutoff of the potentiometer supply points. The cutoff at level of the slider or of the mid point puts Vx out of range.
A low-pass filter of the 2nd order suppresses interference.
Voltage Vx is then multiplexed and digital-encoded.

(b) ANI 2 input - Servocontrol position feedbacks (CAN and MAN boards).
Schematic of interface for one channel*

ANI 2 Input Interface

With V1 = U11 - U12 and V2 = U21 - U22,
the interface performs:
VR = V1 - V2 and VX = V1 + V2.
Voltages VR and Vx are then multiplexed to drive the encoder

Encoder

Using the boards CPU (in COM) or MPU (in MON), the encoder forms a loop which, after successive corrections on VD gives:

VD = VX / VR

ANI 3 Input Interface

The interface performs:
Vs = Vs1 - Vs2 which is then demodulated by a square AC reference.
A low-pass filter of the 2nd order eliminates the signal harmonics.
Voltages Vx are then multiplexed to be digital-encoded.

(d) ANI 4 input - Accelerometers (CAN and MAN boards)
Interface for one input*

ANI 4 Input Interface

The interface performs the differential acquisition of the low-impedance DC signal.
A low-pass filter of the 2nd order suppresses interference.
Voltages Vx are then multiplexed and encoded.

(e) ANO output - servovalve current (CAN board)
The digital value which represents the servovalve current is loaded into the 12-bit DAC of the encoding interface which converts it into an analog voltage VA.
This voltage multiplexed according to the channel, is then memorized in a capacitor which serves, with the next stage, as a sampler/holder.
The output from this stage (VAF) controls the power amplifier, wired as a voltage follower in order to generate the servovalve control current.

Analog Output

(f) ANI 5 inputs - Wraparound of servovalve current (CAN board)
The resistor which programs the servovalve current is divided into two parts.

ANI 5 Input Interface

The intermediate points are internally multiplexed and encoded.
This enables the COM unit to check that the servovalve current is equal to the current that it has controlled.

(g) ANI 7 inputs - Position of solenoid valve selector valves
(MAN boards) Interface for one channel*

ANI 7 Input Interface

The interface performs the differential acquisition of the input which is demodulated, filtered then multiplexed and encoded.

(3) CDG - MDG boards
These boards manage the digital input and output busses to ARINC 429 standard. These boards are identical in COM and in MON.
The first function of this board is to perform the reception, acquisition, recognition and storage of the received messages.
The second function of this board is to perform (upon CPU request) the generation, checking, shaping and transmission of messages on the outputs.
All data exchanged between the CPU and CDG transit via a buffer memory located on the CDG boards.
This memory enables the two microprocessors to perform mutual monitoring.
This board includes:

a 16-bit microprocessor of the 68000 family,
the circuits required for microprocessor starting,
the clock circuits,
a program memory (EPROM : 16 Kwords of 16 bits),
a data memory (SRAM : 2 Kwords of 16 bits),
three timers for program synchronization,
the interrrupt management circuits.

(4) CPS-MPS boards
These cards (CPS in COM and MPS in MON) are identical and perform the functions below

COM Unit Architecture

MON Unit Architecture

generation of voltage sources required for unit operation:
+5V, +/- 15V.
support of discrete outputs and switching relays.

The power supply section includes:

the protection and filtering of interference on the 28VDC.
the conversion of 28V from electrical network into +5V and +/- 15V.
the monitoring:
. of the network voltage : as soon as it is lower than 17V, a P OFF signal is generated.
. of the primary current : a limitation is performed.
. of the +5V at the secondary : as soon as this voltage is higher than 4.75V, a validity signal (P WON) is generated.

The discrete outputs and the relays are managed by the main microprocessor.
Darlington transistor units permit to translate the 5V TTL levels into standard GROUND - OPEN outputs.
Other Darlington transistor units drive the relay coils.

(5) CSP - MSP boards
These boards are identical.
They include:

a 16-bit microprocessor (68000)
one ARINC 429 output (for transmission of information between ELAC1 and ELAC2)
These boards operate as co-processor associated to CPU-MPU boards.

** ON A/C NOT FOR ALL

5. Operation
The ELAC has two independent computation units.

ELAC - Functional Diagram

Each unit performs:

an acquisition and validation of the signals required for its computations.
a computation of the different laws which generate the control surface deflection order (Ref. 27-90).
slaving for the generation of the command current
. in COM for surface slaving
. in MON for monitoring of the orders generated in COM.

A. Monitoring of Peripherals (IMP VAL)
The acquisition and monitoring principles of the signals at the input permit:

a safe operation due to failure detections
a maximum availability due to the reconfigurations further to these failures.

(1) Accelerometer

(a) Architecture

Accelerometer Architecture

Each computer unit receives the values of the load factor measured by 2 accelerometers and the IRS.

(b) Monitoring
Monitoring of the difference between the 2 accelerometers received and elimination of the erroneous accelerometers through comparison of the load factor value from the IRS.
In normal operation, the measured load factor value which is used in the pitch normal law is the half-sum of the two accelerometer signals.

(2) ADIRS

(a) Architecture

ADIRS Architecture

Each computer unit receives the 3 ADIRUs:

2 ADIRUs are directly received by the unit
the 3rd ADIRU comes from the associated unit

(b) Monitoring
Each unit performs the monitorings below:

parity check
refresh rate
status matrix check
monitoring of the 3 alpha probes before takeoff
comparison between signals from the 3 ADIRUs.

In normal operation, the values used in the law computation are:

for the IRUs, the half-sum of the two values from the two IRUs that each unit directly receives.
for the ADRs, the half-sum of the two values from the two ADR 1 and 2.

After one IRU or ADR failure, the value used for the law computation is the half-sum of the two remaining IRUs or ADRs.
Each unit continues to perform the comparison between the remaining values.

The ELACs take into account the IRS mode (NAV mode/ATT mode)

While at least one IRU is seen in NAV mode, an IRU seen in ATT mode is set to the failure state.
When there is no IRU in NAV mode, if at least one IRU is seen in ATT mode, only one of the IRUs in ATT mode is used by the ELACs.
Consequently the ELACs work in alternate law.

(3) Side stick order transducers

(a) Architecture

Side Stick Order Transducer

Each unit receives two signals which give the Captain side stick position in pitch.

one signal comes from the potentiometer directly received by the unit.
the other signal comes from the potentiometer received by the associated unit. REMARK:
An identical architecture is found on the potentiometers which give:
the position of the CAPT side stick in roll,
the position of the F/O side stick in pitch,
the position of the F/O side stick in roll.

(b) Monitorings performed in the ELAC

Monitoring of the encoded value (voltage value of the potentiometer slider) and monitoring of the mid-point voltage of each potentiometer that the unit receives.
Monitoring of the difference between the potentiometer directly received by the associated unit.

(c) Order generation
The side stick order in pitch used in the laws results from the addition of the orders in pitch of the CAPT and F/O side sticks. The side stick order in roll used in the laws results from the mixing of the orders in roll of the CAPT and F/O side sticks.
This mixing is ruled by the priority logic between the two side sticks (CAPT and F/O) (Ref. 27-90).

(4) Rudder pedal transducer unit

(a) Architecture

Rudder Pedal Transducer Unit - Architecture

(b) Monitorings performed in the computer. These are identical with those performed for the side stick order transducers.

(c) Validation logic for rudder position (CAPT and F/O).
the rudder pedal position used for the computation of the control laws is issued from the transducer received by each unit (COM/MON).

(5) Hydraulic pressure transducers

(a) Architecture

Hydraulic Pressure Transducers - Architecture

For each of the 3 hydraulic systems (Blue, Yellow, Green) there is the same architecture is the same.
Each computer unit receives 3 pressure data from each system:

one from a pressure transmitter,
one from a pressure switch directly received by the unit,
one from a pressure switch received by the associated unit.

(b) Monitorings performed in the computer

monitoring of the variation range of each pressure transmitter,
monitoring of each hydraulic pressure switch (by comparison with the transmitter and the other pressure received by the ELAC)
for each hydraulic pressure system : if at least 2 of the 3 pressure data (within one ELAC) detect high pressure (or low pressure) the hydraulic pressure state generated by the ELAC is a high pressure state (or low pressure state).

(6) SFCC

SFCC

(a) Architecture
Each ELAC unit is connected to the SFFC by ARINC 429 buses and hard wired discretes.

(b) Monitoring
Each unit receives 3 types of information:
- One directly from the SFFC
- One from the other unit
- One from the associated unit of the other ELAC.
Each SFCC bus validity is produced by the following monitorings:

SSM
Refresh/Parity
Comparison between bus information and discrete input

Boolean information of each source are compared. If at least two types of validated information are in agreement, this data is used for computation.

(7) Radio altimeter (RA)

(a) Architecture
The same radio-altimeter ARINC 429 output is connected to the two ELACs. The COM units of each ELAC receive RA1, the MON units receive RA2, the values directly received are exchanged by the COM/MON buses.

(b) Monitoring
Validity of each bus is produced (on label 164) by the monitorings below:

SSM
Refresh/Parity
Coherence monitoring: a RA is definitively eliminated for law computation if, while Vc is higher than 200 Kts, it gives HRA value lower than 50 ft.

Information from the different sources are compared. If a disagree appears,the altitude is set at a value higher than 200 ft (except if the full slat/flap configuration is seen for 10 s minimum).

If only one RA is valid:

The altitude is set at a value higher than 200 ft is the speed is higher than 180 kts.

If no RA is valid:

The altitude is set at a value higher than 200 ft.

(8) Servocontrol position transducers

Servocontrol Position Transducer - Architecture

The two monitorings below are performed for each servocontrol position transducer:

Monitoring of the variation range of the value that the transducer supplies.
Monitoring of the reference voltage that the transducer supplies.

(9) Solenoid valve position transducer

Position Transducers of the Solenoid Valve Servovalves Architecture

The monitorings below are performed for the solenoid valve position transducers:

Monitoring of transducer operating range.
Monitoring of consistency of selector valve position.

This monitoring consists in checking that the servovalve position corresponds to the commanded operating mode (active or damping mode).

(10) THS Monitoring

THS Slaving in the ELACs

The monitoring of THS slaving relays K3 is performed when:

the hydraulic systems are depressurized
the aircraft is on ground
the side sticks are at neutral
and it is launched after each ELAC reset (circuit breaker or pushbutton).

B. Computation of Laws
The laws are described in 27-90.

C. Control Surface Slaving
The ELACs perform slaving of the two elevators, one THS actuator electric motor and the 2 ailerons, according to specific laws.

(1) Elevator slaving

Elevator Servocontrol Slaving in the ELAC

The COM unit in the computers performs three main functions:

generation of command current
monitoring of this current through internal wraparound
slaving engage logic.
monitoring of the servo valve spool valve transducer
In the MON unit, the slaving monitoring consists in monitoring the correct servovalve spool valve position (comparison beween the servo valve current commanded by COM and the spool valve position transducer received by MON).

(2) THS slaving

THS Slaving in the ELACs

The COM unit of the computers performs three main functions:

THS slaving which controls the electric motor.
Monitoring of the control current.

NOTE: When the concerned computer is not in charge of the THS slaving, the slaving order is synchronized on the actual position of the THS.

the slaving engage logic by relays K3 and K12 which cut off the motor current.

In the MON unit, the monitoring of the THS position is made through comparison of the actual position with the theoretical position.
The theoretical position is computed through the use of "images" of the electric and hydraulic motors.
In addition an encoded value of THS position dedicated to COM unit is sent to the MON unit which performs a permanent comparison with its own encoded value.
The monitorings are active only if the slaving is engaged.

(3) Aileron slaving

Aileron Servocontrol Slaving

In the COM unit of the ELACs, there are two main functions:

slaving proper with generation of the servovalve current.
monitoring of the generated current through internal wraparound of the servovalve current.

In the MON unit, the two functions below ensure the aileron monitoring:

comparison between the deviation signal of the monitoring channel and the servovalve current received from the COM unit.
comparison between the aileron position and an order generated in MON.
In the damping servocontrol, a constant current (-2mA) is sent to the servovalve.

D. Self-Monitoring of the Computer
The monitorings below are incorporated in the ELAC independently of the functions performed by software.

(1) Watchdog

(a) Watchdog main processor
A "hardware" watchdog re-activates the microprocessor further to an internal failure.
This watchdog is actuated by a software command.

(b) ARINC processor watchdog
Ditto

(c) Discrete output watchdog
A "hardware" watchdog directly cuts off the discrete outputs and relays if it is not regulary re-started by the main processor.

(d) Bus monitoring
The correct operation of the bus of the digital section is monitored.
Upon triggering of this monitoring, the processor is stopped until it is restarted by the watchdog (Ref. Para. (a)).

(2) Power supply monitoring

5V : permanently monitored by a "hardware" comparator.
transducer supply voltage and 15VDC : permanently monitored and encoded (software comparator).

(3) Permanent software monitorings
Software monitorings are performed as "background tasks":

checksum computations of the program memories.
crossed monitoring between the processors of a same unit which use the dual-access memories.
Monitoring of the co-processor by the main processor
Mutual monitoring of the main processor/ARINC processor : the ARINC processor can directly cut off all the discrete outputs and relays.

(4) Quartz clock monitoring
Each of the ARINC and main processors has its own quartz clock.
A "hardware" comparator permits to detect any relative variation between the two clocks.

(5) Inter-unit monitoring
Two ARINC 429 links are dedicated to crosstalk between the two units.
The monitoring is made at software level and consists in the comparison of variables which transit on these buses.

E. Behavior upon Power Rise and Cutoff

ELAC Behavior Upon Power Supply Rise

(1) Transparency
The computer behavior is not altered if its power supply disappears for a period less than or equal to 20 ms.

(2) Startup
If the power supply is absent for more than 20 ms, two cases are considered:

(a) If at least one hydraulic supply is present, the computer starts after it has performed short tests (duration <1.5 s ):

timer test
interrupt test
RAM partial test

(b) If the 3 hydraulic power supplies are low, two cases are considered:
1- Power supply switch-off less than 3s, the short test is performed (see (a))
2- Power supply switch-off during more than 3s, the long test is performed :

UC test
watchdog test
checksum test
complete RAM test
timer test
IT test
bus error test

F. Behavior upon Action on the OFF/R Pushbutton Switch

ELAC Behavior Upon Pushbutton Reset

In normal configuration, the pushbutton switch is pushed. The change from OFF to ON (startup) when the power supply is present leads to computer startup:

if 1 hydraulic pressure is high : short test
if 3 hydraulic pressures are low : long test

[Rev.10 from 2021] 2026.04.01 08:39:12 UTC