DOC AIRBUS | AMM A320FDISPLAY MANAGEMENT COMPUTER (DMC) - DESCRIPTION AND OPERATION
** ON A/C NOT FOR ALL
** ON A/C NOT FOR ALL
1. General
The Display Management Computer (DMC) is a part of the EIS (Electronic Instrument System). It receives data from different avionics systems in the aircraft, decodes it. It also processes it in such a way so that the connected full color Display Units (DUs) in the cockpit can use it in order to generate symbols and pictures on their CRT displays. The DMC can drive three DUs simultaneously - two EFIS DUs and any one of the two ECAM DUs.
Memory modules mounted in a dog-house on the face of the unit facilitate operational software changes in the unit.
** ON A/C NOT FOR ALL The Display Management Computer (DMC) is a part of the EIS (Electronic Instrument System). It receives data from different avionics systems in the aircraft, decodes it. It also processes it in such a way so that the connected full color Display Units (DUs) in the cockpit can use it in order to generate symbols and pictures on their CRT displays. The DMC can drive three DUs simultaneously - two EFIS DUs and any one of the two ECAM DUs.
Memory modules mounted in a dog-house on the face of the unit facilitate operational software changes in the unit.
Overhall Architecture2. Component location
** ON A/C NOT FOR ALL | FIN | FUNCTIONAL DESIGNATION | PANEL | ZONE | ACCESS DOOR | ATA REF |
|---|---|---|---|---|---|
| ** ON A/C NOT FOR ALL | |||||
| 1WT1 | DMC-1 | 85VU | 127 | 31-63-34 | |
| 1WT2 | DMC-2 | 86VU | 128 | 31-63-34 | |
| 1WT3 | DMC-3 | 85VU | 127 | 31-63-34 | |
| 2WT1 | PFD-CAPT | 3VU | 211 | 31-63-22 | |
| 2WT2 | PFD-F/O | 5VU | 212 | 31-63-22 | |
| 3WT1 | ND-CAPT | 3VU | 211 | 31-63-22 | |
| 3WT2 | ND-F/O | 5VU | 212 | 31-63-22 | |
| 4WT1 | DU-ECAM, UPPER | 4VU | 210 | 31-63-22 | |
| 4WT2 | DU-ECAM, LOWER | 4VU | 210 | 31-63-22 | |
3. System Description
A. DMC
The DMC is contained in a 6 MCU main housing, which can hold nine slide-in type electronic boards (seven used, two spares), a slide-in type power supply module and a dog-house mounted on its face.
The seven slide-in type electronic boards are as follows:
Each memory module, which consists of a separate housing containing a PCB (printed circuit board), can be individually removed from the dog-house by means of two clips. The housing has an identification, a name plate and a PCB which holds the memory units.
The additional boards - protection boards 1 and 2 - are mounted on the mother board inside the DMC.
The mother board provides inter-connections between the various boards, the power supply module and the ARINC 600 connector. The ARINC 600 connector is mounted on the rear side of the main housing of the unit.
The DMC is contained in a 6 MCU main housing, which can hold nine slide-in type electronic boards (seven used, two spares), a slide-in type power supply module and a dog-house mounted on its face.
The seven slide-in type electronic boards are as follows:
- DPU 1 (PFD) board
- DPU 2 (ND) board
- DPU 3 (ECAM) board
- I/O interface 1 board
- I/O interface 2 board
- I/O interface 3 board
- W/R board.
- Regulator/generator board
- Controller/monitor board
- Filter board.
Each memory module, which consists of a separate housing containing a PCB (printed circuit board), can be individually removed from the dog-house by means of two clips. The housing has an identification, a name plate and a PCB which holds the memory units.
The additional boards - protection boards 1 and 2 - are mounted on the mother board inside the DMC.
The mother board provides inter-connections between the various boards, the power supply module and the ARINC 600 connector. The ARINC 600 connector is mounted on the rear side of the main housing of the unit.
B. CRT
The display unit consists of the following sub-assemblies:
The display unit consists of the following sub-assemblies:
- Cathode ray tube (CRT) assembly; it includes:
. a high resolution color CRT (Shadow-mask type) with electrostatic focus and electromagnetic deflection,
. deflection yokes,
. magnetic shield. - Very high voltage (VHV) power supply:
It provides all the potentials necessary for the CRT (anode, focus and G2 electrodes). - One analog board; it includes:
. deflection amplifiers,
. convergence circuits,
. video amplifiers,
. brightness control,
. monitoring circuits. - One symbol generator (SG) block
- Interconnection board:
It realizes the interconnection between the DU and the DMC and, inside the DU, between the SG board, the analog board and the power supply. - Low voltage (LV) power supply:
The low voltage power supply is supplied with 115V - 400 Hz from the aircraft electrical power.
4. Interface
(Ref. ATA 31-62-00-WT)
** ON A/C NOT FOR ALL (Ref. ATA 31-62-00-WT)
5. Component Description
A. DMC
(1) General
(a) System operation
The configuration of the three DMCs and the six DUs in the EIS ensures redundancy, thanks to switching capabilities of individual DMCs to the DUs.
The three DMCs are identical and therefore interchangeable.
During normal operation:
In case of a breakdown of a DU, the DMC channel which drives this DU is switched to the alternate channel of another DU , which undertakes the task of the failed DU.
The configuration of the three DMCs and the six DUs in the EIS ensures redundancy, thanks to switching capabilities of individual DMCs to the DUs.
The three DMCs are identical and therefore interchangeable.
During normal operation:
- DMC1 drives CAPT PFD, CAPT ND and upper ECAM DU
- DMC2 drives F/O PFD, F/O ND and lower ECAM DU
- DMC3 is a back up (hot spare) unit.
In case of a breakdown of a DU, the DMC channel which drives this DU is switched to the alternate channel of another DU , which undertakes the task of the failed DU.
(b) DMC operation
The DMC can be divided into four basic sections:
The I/O interface 1 to 3 boards and the WXR (weather radar) board in the unit are responsible for accomplishing this task. The hardware contents of the three I/O interface boards are almost identical ; they differ, however, in their software contents.
The data acquisition section can handle 60 discrete inputs, 54 ARINC 429 inputs, 4 WXR channels, 3 RS 422 data link inputs and 6 RS 232C data link inputs as well as 12 discrete outputs and 3 ARINC 429 outputs. The discrete input signals, which define system-commands, are received by the I/O interface boards, and each signal is transformed into 2 x 16-bit words. These words are then routed to the COMMON RAM (located on the DPU 1 (PFD) board), where they are stored in their appropriate locations for use by the DPU boards. The ARINC 429 input (high or low speed) signals, which represent navigational information, are also received by the I/O interface boards. They are checked for validity and if valid, relabelled and stored in the COMMON RAM in their appropriate locations for use by the DPU boards. The RS 422 data link inputs, which represent texts/ messages, etc. generated by the FWC and to be displayed on the ECAM DU, are received serially by the I/O interface boards. They are converted into parallel bits and stored in the COMMON RAM for use by the DPU 3 (ECAM) board. The RS 232C data the COMMON RAM for use by the DPU 3 (ECAM) board. The RS 232C data link inputs (one each to the three I/O interface boards and the three DPU boards) are used for maintenance purposes only. The discrete output signals generated in the DMC and which represent validity signals for each channel (PFD, ND, ECAM), etc. as well as ARINC 429 output signals (2 low speed and 1 high speed) also generated in the DMC are fetched from the COMMON RAM under control of a DPU board and routed to external avionics systems via the I/O interface board.
Four input channels as per ARINC 453 specifications feed WXR data from the weather radar transceiver to the WXR board; the WXR data format conforms with the ARINC 708 specification.The data is processed on this board, under the control of the DPU 2 (ND) to draw a color WXR map on the ND, which shows the weather conditions in front of the aircraft.
The main function of each of the three independent channels - PFD, ND and ECAM - is to process the relevant input signals received by the data acquisition section and prepare data, which can be used by the DUs to draw the required symbols or pictures simultaneously. The processors on the boards DPU1 (PFD), DPU2 (ND) and DPU3 (ECAM) perform this function. All three boards are almost identical in hardware contents (except for the DPU1 (PFD), which contains the COMMON RAM, the BITE memory and the bus arbiter contains the COMMON RAM, the BITE memory and the bus arbiter additionally); they differ, however, in the software implemented on.
The other functions of the processors on the DPU boards are :
Each board (I/O or DPU) can send an independent bus-request (BR*) signal to the bus arbiter (located on the DPU1 (PFD) board). The bus arbiter grants this request with a fairness protocol and sends a corresponding bus-grant (BG IN*) signal to the particular board. The board can now use the COMMON BUS (signal busy* is asserted). The power supply module, operating on 115v/400Hz aircraft supply voltage and controlled by the signal POWER DOWN, supplies all internal voltages in the unit.
The DMC can be divided into four basic sections:
- data acquisition
- PFD channel
- ND channel
- ECAM channel.
The I/O interface 1 to 3 boards and the WXR (weather radar) board in the unit are responsible for accomplishing this task. The hardware contents of the three I/O interface boards are almost identical ; they differ, however, in their software contents.
The data acquisition section can handle 60 discrete inputs, 54 ARINC 429 inputs, 4 WXR channels, 3 RS 422 data link inputs and 6 RS 232C data link inputs as well as 12 discrete outputs and 3 ARINC 429 outputs. The discrete input signals, which define system-commands, are received by the I/O interface boards, and each signal is transformed into 2 x 16-bit words. These words are then routed to the COMMON RAM (located on the DPU 1 (PFD) board), where they are stored in their appropriate locations for use by the DPU boards. The ARINC 429 input (high or low speed) signals, which represent navigational information, are also received by the I/O interface boards. They are checked for validity and if valid, relabelled and stored in the COMMON RAM in their appropriate locations for use by the DPU boards. The RS 422 data link inputs, which represent texts/ messages, etc. generated by the FWC and to be displayed on the ECAM DU, are received serially by the I/O interface boards. They are converted into parallel bits and stored in the COMMON RAM for use by the DPU 3 (ECAM) board. The RS 232C data the COMMON RAM for use by the DPU 3 (ECAM) board. The RS 232C data link inputs (one each to the three I/O interface boards and the three DPU boards) are used for maintenance purposes only. The discrete output signals generated in the DMC and which represent validity signals for each channel (PFD, ND, ECAM), etc. as well as ARINC 429 output signals (2 low speed and 1 high speed) also generated in the DMC are fetched from the COMMON RAM under control of a DPU board and routed to external avionics systems via the I/O interface board.
Four input channels as per ARINC 453 specifications feed WXR data from the weather radar transceiver to the WXR board; the WXR data format conforms with the ARINC 708 specification.The data is processed on this board, under the control of the DPU 2 (ND) to draw a color WXR map on the ND, which shows the weather conditions in front of the aircraft.
The main function of each of the three independent channels - PFD, ND and ECAM - is to process the relevant input signals received by the data acquisition section and prepare data, which can be used by the DUs to draw the required symbols or pictures simultaneously. The processors on the boards DPU1 (PFD), DPU2 (ND) and DPU3 (ECAM) perform this function. All three boards are almost identical in hardware contents (except for the DPU1 (PFD), which contains the COMMON RAM, the BITE memory and the bus arbiter contains the COMMON RAM, the BITE memory and the bus arbiter additionally); they differ, however, in the software implemented on.
The other functions of the processors on the DPU boards are :
- process status information fetched from the COMMON RAM
- react to various interrupts
- provide the frame time for the stroke picture or for the WXR picture (DPU2 (ND) only) on the respective DU
- control the digital output link to the DU
- run test routines
- generate maintenance information
- control WRX beam information (DPU2 (ND) only).
Each board (I/O or DPU) can send an independent bus-request (BR*) signal to the bus arbiter (located on the DPU1 (PFD) board). The bus arbiter grants this request with a fairness protocol and sends a corresponding bus-grant (BG IN*) signal to the particular board. The board can now use the COMMON BUS (signal busy* is asserted). The power supply module, operating on 115v/400Hz aircraft supply voltage and controlled by the signal POWER DOWN, supplies all internal voltages in the unit.
(2) Functional description
The functional description of all the boards and the power supply module in the DMC is dealt with in this chapter.
The functional description of all the boards and the power supply module in the DMC is dealt with in this chapter.
(a) DPU1 (PFD), DPU2 (ND), DPU3 (ECAM) boards
The general function of all three boards is identical. Each board can operate independently as it contains its own CPU and memory. The design of the board is based on the MC 68020 (CPU) concept, which enables the use of a powerful instruction set. Its RAM consists of the local RAM and the COMMON RAM (located on the DPU1 (PFD) board).
The access to the COMMON RAM, however, is via the COMMON BUS and hence the priority rules apply.
Its whole ROM is located on the OBRM. This means that the complete software of each DPU is located on the OBRM.
The main tasks of each DPU board are:
The general function of all three boards is identical. Each board can operate independently as it contains its own CPU and memory. The design of the board is based on the MC 68020 (CPU) concept, which enables the use of a powerful instruction set. Its RAM consists of the local RAM and the COMMON RAM (located on the DPU1 (PFD) board).
The access to the COMMON RAM, however, is via the COMMON BUS and hence the priority rules apply.
Its whole ROM is located on the OBRM. This means that the complete software of each DPU is located on the OBRM.
The main tasks of each DPU board are:
- data processing, which includes scaling, filtering and execution of mathematical and logical functions
- control of the DUs i.e. preparation of their input data, basic timing as well as start-, verify- and switching operations
- execution of a part of the BITE (built-in test equipment) and fault isolation. The BITE memory is located on the DPU1 (PFD) board and can be accessed via the COMMON BUS.
- Central Processing Unit (CPU)
- local RAM and system EPROM
- watch dog timer, address decoder and interrupt logic
- bus requester and bus couplers
- COMMON BUS time out control
- MFPI
- MFPII
- DSDL control logic
- COMMON RAM, BITE memory and bus arbiter
1 Central Processing Unit (CPU)
The CPU is a 32-bit microprocessor from the MC68020 family. It is always in one of the following three processing states:
The CPU is a 32-bit microprocessor from the MC68020 family. It is always in one of the following three processing states:
- normal processing state, which is associated with instruction execution. In this state, the CPU fetches instructions/operands from its own system EPROM or from the COMMON RAM, processes them and stores the final result back in the COMMON RAM
- execution processing state, which is associated with interrupts, trap instructions, tracing and other exceptional conditions. In this case, a vector number, which is fetched from the system EPROM, is fed to the CPU via the LOCAL-DATA-BUS. The vector number is processed in the CPU and relevant addresses are sent to fetch the necessary instruction from the system EPROM. The CPU executes this instruction in order to carry out the necessary operation
- halted processing state, which is an indication of a catastrophic hardware failure. For example, if during the exception processing of a bus-error another bus-error occurs, the CPU assumes that the system is unusable and halts.
2 Local RAM and system EPROM
When the CPU is in one of its three processing states, it requires intermediate storing facility for data/results. This is provided by the 32 K x 16 bit local RAM. It is addressed by the LOCAL-ADDRESS-BUS and data transfer takes place via the LOCAL-DATA-BUS. It is enabled by an address decoder and the read/write signals are provided by the CPU via the R/W logic.
The local RAM has a special power supply line (+5 V PROT.). This provides continuous power to the local RAM even during a short-power-interrupt condition. This same line provides power to the COMMON RAM (on DPU1 (PFD) board) also.
The system EPROM consists of program EPROMs and data EPROMs. The program EPROMs contain instructions required by the CPU to execute the operational program. They also contain a test library and a monitoring program for maintenance purposes, which monitor the system hardware, depending on the information received via the RS 232 serial interface. The data EPROMs contain data required by the CPU while executing the operational program.
Those program EPROMs and data EPROMs, which contain the operational software, are located in the OBRM in the dog-house mounted on the front side of the unit.
Those program EPROMs and data EPROMs are located on the OBRM which consists of a 128K x 32 bit EPROM bank.
When the CPU is in one of its three processing states, it requires intermediate storing facility for data/results. This is provided by the 32 K x 16 bit local RAM. It is addressed by the LOCAL-ADDRESS-BUS and data transfer takes place via the LOCAL-DATA-BUS. It is enabled by an address decoder and the read/write signals are provided by the CPU via the R/W logic.
The local RAM has a special power supply line (+5 V PROT.). This provides continuous power to the local RAM even during a short-power-interrupt condition. This same line provides power to the COMMON RAM (on DPU1 (PFD) board) also.
The system EPROM consists of program EPROMs and data EPROMs. The program EPROMs contain instructions required by the CPU to execute the operational program. They also contain a test library and a monitoring program for maintenance purposes, which monitor the system hardware, depending on the information received via the RS 232 serial interface. The data EPROMs contain data required by the CPU while executing the operational program.
Those program EPROMs and data EPROMs, which contain the operational software, are located in the OBRM in the dog-house mounted on the front side of the unit.
Those program EPROMs and data EPROMs are located on the OBRM which consists of a 128K x 32 bit EPROM bank.
3 Watch dog timer, address decoder and interrupt logic
The watch dog timer, which is integrated into a gate array, continuously monitors the trigger-watchdog-flag TRW* from the Control register at intervals determined by a clock from the clock generator. In case the flag TRW* remains inactive for a period longer than 100 ms (which happens if an error occurs during the normal processing state of the CPU), the watch dog timer generates a watchdog-reset (WDR*) signal. This activates the reset logic (also in a gate array), which resets the CPU. The address decoder decodes the addresses on the LOCAL-ADDRESS-BUS and outputs various control-enable signals for the other functional blocks on the board.
For example, the control-enable signal CE EPR, enables a read-out from the EPROM section ; or control-enable signal CE BUS enables the COMMON BUS time out control and so on.
The interrupt logic determines the interrupt-priority level (IPL) for the interrupt inputs, which are requesting an interrupt in the CPU operation. The interrupt-request-inputs are received from MFPI and MFPII (Ref. Para. 5.A.(2)(a)6). When an interrupt is granted, the CPU sends out function-code-output (FCO) signals back to the interrupt logic, which activates the interrupt acknowledge signal in order to inform MFPI or MFPII that an interrupt has been granted.
The watch dog timer, which is integrated into a gate array, continuously monitors the trigger-watchdog-flag TRW* from the Control register at intervals determined by a clock from the clock generator. In case the flag TRW* remains inactive for a period longer than 100 ms (which happens if an error occurs during the normal processing state of the CPU), the watch dog timer generates a watchdog-reset (WDR*) signal. This activates the reset logic (also in a gate array), which resets the CPU. The address decoder decodes the addresses on the LOCAL-ADDRESS-BUS and outputs various control-enable signals for the other functional blocks on the board.
For example, the control-enable signal CE EPR, enables a read-out from the EPROM section ; or control-enable signal CE BUS enables the COMMON BUS time out control and so on.
The interrupt logic determines the interrupt-priority level (IPL) for the interrupt inputs, which are requesting an interrupt in the CPU operation. The interrupt-request-inputs are received from MFPI and MFPII (Ref. Para. 5.A.(2)(a)6). When an interrupt is granted, the CPU sends out function-code-output (FCO) signals back to the interrupt logic, which activates the interrupt acknowledge signal in order to inform MFPI or MFPII that an interrupt has been granted.
4 Bus requester and bus couplers
When the CPU on any DPU board wants access to the COMMON BUS, it puts in a request through the bus requester, integrated in a gate-array, which processes signals mainly obtained from the CPU. It generates a bus-request (BR*) signal, which is sent to the bus arbiter (located on the DPU1 (PFD) board). When the bus request is granted, the bus arbiter sends a bus-grant (BG IN*) signal back to the bus requester, which enables the bus couplers on the board and also asserts a busy signal (BUSY*) in order to inform the bus arbiter that the COMMON BUS is now being used.
There are three types of bus couplers on each board - the LOCAL-DATA- BUS couplers, the LOCAL-ADDRESS-BUS couplers and the LOCAL-CONTROL- BUS couplers. These bus couplers enable data transfer between the local buses on the board and the COMMON BUS. The DPU1 (PFD) board has three additional bus couplers - the MEMORY-DATA-BUS couplers, the MEMORY-ADDRESS-BUS couplers and the MEMORY- CONTROL-BUS couplers.
These bus couplers enable data transfer between the memory buses on the board and the COMMON BUS.
When the CPU on any DPU board wants access to the COMMON BUS, it puts in a request through the bus requester, integrated in a gate-array, which processes signals mainly obtained from the CPU. It generates a bus-request (BR*) signal, which is sent to the bus arbiter (located on the DPU1 (PFD) board). When the bus request is granted, the bus arbiter sends a bus-grant (BG IN*) signal back to the bus requester, which enables the bus couplers on the board and also asserts a busy signal (BUSY*) in order to inform the bus arbiter that the COMMON BUS is now being used.
There are three types of bus couplers on each board - the LOCAL-DATA- BUS couplers, the LOCAL-ADDRESS-BUS couplers and the LOCAL-CONTROL- BUS couplers. These bus couplers enable data transfer between the local buses on the board and the COMMON BUS. The DPU1 (PFD) board has three additional bus couplers - the MEMORY-DATA-BUS couplers, the MEMORY-ADDRESS-BUS couplers and the MEMORY- CONTROL-BUS couplers.
These bus couplers enable data transfer between the memory buses on the board and the COMMON BUS.
5 COMMON BUS time out control
This logic, which is integrated in a gate array, determines how long its CPU can claim access to the COMMON BUS. The time interval begins with signal CE BUS* going active i.e. when the CPU has gained access to the COMMON BUS, and the timing is monitored by a clock from the clock generator. On completion of the specified time interval, a signal BERR* is activated to stop the CPU.
This logic, which is integrated in a gate array, determines how long its CPU can claim access to the COMMON BUS. The time interval begins with signal CE BUS* going active i.e. when the CPU has gained access to the COMMON BUS, and the timing is monitored by a clock from the clock generator. On completion of the specified time interval, a signal BERR* is activated to stop the CPU.
6 MFPI
MFPI (multi-function peripheral) is a 48-pin integrated module containing the following main functional groups:
The GPIP receives interrupt-requests (IRQ*) from external devices as well as from the DSDL control logic (TX/R) and routes these to the interrupt controller I. The source of the interrupt-requests from external devices varies on each DPU board.
The interrupt controller I handles the interrupt requests received via the GPIP as well as those generated by certain functional blocks inside MFPI. It uses the daisy-chaining principle and as per the priority rules, sends the signal INT MFPI* to the interrupt logic in order to request an interrupt in the CPU operation on the board.
The IT generator 1 is a real time monitor and generates definite cycles, during which the CPU can execute various management tasks.
The IT generator 2 is a frame time monitor and also generates definite cycles, during which specific routines can be executed on the DUs. In order to perform these operations, both IT generators transmit an interrupt-request each to the interrupt controller I.
The serial interface I is basically a UART (Universal Asynchronous Receiver Transmitter). It provides asynchronous serial communication with an external device (e.g. a debugger) during maintenance operations.
MFPI (multi-function peripheral) is a 48-pin integrated module containing the following main functional groups:
- general purpose I/O port (GPIP)
- interrupt controller I
- IT generators 1 and 2
- serial interface I.
The GPIP receives interrupt-requests (IRQ*) from external devices as well as from the DSDL control logic (TX/R) and routes these to the interrupt controller I. The source of the interrupt-requests from external devices varies on each DPU board.
The interrupt controller I handles the interrupt requests received via the GPIP as well as those generated by certain functional blocks inside MFPI. It uses the daisy-chaining principle and as per the priority rules, sends the signal INT MFPI* to the interrupt logic in order to request an interrupt in the CPU operation on the board.
The IT generator 1 is a real time monitor and generates definite cycles, during which the CPU can execute various management tasks.
The IT generator 2 is a frame time monitor and also generates definite cycles, during which specific routines can be executed on the DUs. In order to perform these operations, both IT generators transmit an interrupt-request each to the interrupt controller I.
The serial interface I is basically a UART (Universal Asynchronous Receiver Transmitter). It provides asynchronous serial communication with an external device (e.g. a debugger) during maintenance operations.
7 MFPII
The basic operation of MFPII is similar to that of MFPI. The GPIP, in this case, receives various signals as well as activates output signals. The number of input and output signals varies on each DPU board. Some of the input signals are routed to the interrupt controller II and can claim an interrupt in the CPU operation on the board. The other input signals are status-signals and inform the CPU of the status of their sources.
The operation of the interrupt controller in MFPII is similar to that in MFPI. It sends the signal INT MFPII* to the interrupt logic in order to request an interrupt in the CPU operation on the board.
There is a real time counter and a baudrate timer in MFPII. The real time counter operates in the event-counting mode and the baudrate timer generates two baudrate clocks : BDRCK SI I for the serial interface I in MFPI and one for the serial interface II in MFPII.
The serial interface in MFPII has the same function as that in MFPI and is used during maintenance operations.
The basic operation of MFPII is similar to that of MFPI. The GPIP, in this case, receives various signals as well as activates output signals. The number of input and output signals varies on each DPU board. Some of the input signals are routed to the interrupt controller II and can claim an interrupt in the CPU operation on the board. The other input signals are status-signals and inform the CPU of the status of their sources.
The operation of the interrupt controller in MFPII is similar to that in MFPI. It sends the signal INT MFPII* to the interrupt logic in order to request an interrupt in the CPU operation on the board.
There is a real time counter and a baudrate timer in MFPII. The real time counter operates in the event-counting mode and the baudrate timer generates two baudrate clocks : BDRCK SI I for the serial interface I in MFPI and one for the serial interface II in MFPII.
The serial interface in MFPII has the same function as that in MFPI and is used during maintenance operations.
8 DSDL control logic
The DSDL (Dedicated Serial Data Link) control logic on a DPU board is responsible for a data transfer between that board and its dedicated DU. It sends data to the stroke generator, located inside the DU, and receives data from the DU to test the data-link as well as the stroke generator inside this DU. After power-on or after changing the DU picture mode, the stroke generator program is loaded from the DPU board in the DU and verified. The results of the selftest routines inside the DU are sent back to the DPU boards.
The DSDL control logic consists mainly of the DSDL interface and the DSDL switching circuit.
The DSDL interface, which consists of a transmitter-and a receiver-section, enables the bidirectional data transfer between the board and the DU. The DU-specific data processed on the board is parallel-to-series converted by the transmitter-section in the DSDL interface and transmitted to the DU via the DSDL transmitter and the DSDL switching circuit. The test-related data from the DU is series-to-parallel converted by the receiver-section in the DSDL interface and is processed accordingly by the CPU.
The enabling of the transmitter-section and the selection of the receiver-section in the DSDL interface is executed by the control register and the select logic respectively.
The DSDL switching circuit is different on the three DPU boards.
It consists basically of two relay units ; each unit having a double-pole two-way switching capability. During normal operation, the relay-units are not activated. A bidirectional data transfer between this DMC and the DU thus takes place. In the case of a breakdown of this DMC, one relay-unit is activated by the external signal DMC3 TRANSFER, and a bidirectional data transfer between the back-up DMC3 and the relevant DU takes place. In the case of a breakdown of an ECAM DU, the second relay-unit is activated by the external signal ND/ECAM TRANSFER and a bidirectional data transfer between an EFIS DU and the DPU3 (ECAM) board (via DPU2 (ND) board) takes place.
The DSDL (Dedicated Serial Data Link) control logic on a DPU board is responsible for a data transfer between that board and its dedicated DU. It sends data to the stroke generator, located inside the DU, and receives data from the DU to test the data-link as well as the stroke generator inside this DU. After power-on or after changing the DU picture mode, the stroke generator program is loaded from the DPU board in the DU and verified. The results of the selftest routines inside the DU are sent back to the DPU boards.
The DSDL control logic consists mainly of the DSDL interface and the DSDL switching circuit.
The DSDL interface, which consists of a transmitter-and a receiver-section, enables the bidirectional data transfer between the board and the DU. The DU-specific data processed on the board is parallel-to-series converted by the transmitter-section in the DSDL interface and transmitted to the DU via the DSDL transmitter and the DSDL switching circuit. The test-related data from the DU is series-to-parallel converted by the receiver-section in the DSDL interface and is processed accordingly by the CPU.
The enabling of the transmitter-section and the selection of the receiver-section in the DSDL interface is executed by the control register and the select logic respectively.
The DSDL switching circuit is different on the three DPU boards.
It consists basically of two relay units ; each unit having a double-pole two-way switching capability. During normal operation, the relay-units are not activated. A bidirectional data transfer between this DMC and the DU thus takes place. In the case of a breakdown of this DMC, one relay-unit is activated by the external signal DMC3 TRANSFER, and a bidirectional data transfer between the back-up DMC3 and the relevant DU takes place. In the case of a breakdown of an ECAM DU, the second relay-unit is activated by the external signal ND/ECAM TRANSFER and a bidirectional data transfer between an EFIS DU and the DPU3 (ECAM) board (via DPU2 (ND) board) takes place.
9 COMMON RAM, BITE memory and bus arbiter
The COMMON RAM, the BITE memory and the bus arbiter are located on the DPU1 (PFD) board only. The COMMON RAM and the BITE memory are accessible to the DPU and I/O boards through the COMMON BUS.
The COMMON RAM has a storage capacity for 16Kx16-bit words. It is divided into definite sections, where computed data from the DPU and I/O boards is stored intermediately until further use. It is addressed by the MEMORY-ADDRESS-BUS and data transfer takes place through the MEMORY-DATA-BUS. The memory address decoder provides the control-signals for the COMMON RAM. A special power supply line +5 V PROT. from the power supply module provides continuous power to the COMMON RAM even during a short-power-interrupt condition.
The BITE memory has a total storage capacity of 2Kx16-bit words.
A fault indication from any board during a self-test routine is stored in this memory for analysis during maintenance operations. It is accessed in the same manner as the COMMON RAM.
The bus arbiter can receive four bus-request (BR*) signals simultaneously for the use of the COMMON BUS - three from the three I/O interface boards and one from the three DPU boards, which are daisy-chained. Based on the priority rules, the bus arbiter then grants request to that board with the highest priority-level. This is done by activating the specific bus-grant signal (BGIN*). The bus arbiter can transmit four bus grant signals - three to the three I/O interface boards and one to the three daisy-chained DPU boards. Once a bus-request is granted to a board, it asserts the signal BUSY* which informs the bus arbiter that the COMMON BUS is being used.
The bus arbiter can treat 6 bus-requests (BR*) with priority and fairness protocol.
Fairness: If 3 or more bus requests occur at the same time, all requests will be granted in priority sequence without interruption.
The maximum waiting time of a requesting device is the duration of 5 common bus cycles incl. arbitration.
The COMMON RAM, the BITE memory and the bus arbiter are located on the DPU1 (PFD) board only. The COMMON RAM and the BITE memory are accessible to the DPU and I/O boards through the COMMON BUS.
The COMMON RAM has a storage capacity for 16Kx16-bit words. It is divided into definite sections, where computed data from the DPU and I/O boards is stored intermediately until further use. It is addressed by the MEMORY-ADDRESS-BUS and data transfer takes place through the MEMORY-DATA-BUS. The memory address decoder provides the control-signals for the COMMON RAM. A special power supply line +5 V PROT. from the power supply module provides continuous power to the COMMON RAM even during a short-power-interrupt condition.
The BITE memory has a total storage capacity of 2Kx16-bit words.
A fault indication from any board during a self-test routine is stored in this memory for analysis during maintenance operations. It is accessed in the same manner as the COMMON RAM.
The bus arbiter can receive four bus-request (BR*) signals simultaneously for the use of the COMMON BUS - three from the three I/O interface boards and one from the three DPU boards, which are daisy-chained. Based on the priority rules, the bus arbiter then grants request to that board with the highest priority-level. This is done by activating the specific bus-grant signal (BGIN*). The bus arbiter can transmit four bus grant signals - three to the three I/O interface boards and one to the three daisy-chained DPU boards. Once a bus-request is granted to a board, it asserts the signal BUSY* which informs the bus arbiter that the COMMON BUS is being used.
The bus arbiter can treat 6 bus-requests (BR*) with priority and fairness protocol.
Fairness: If 3 or more bus requests occur at the same time, all requests will be granted in priority sequence without interruption.
The maximum waiting time of a requesting device is the duration of 5 common bus cycles incl. arbitration.
(b) I/O interface 1, 2 and 3 boards
Each of the three interface boards consists of three independent I/O (input/output) interfaces:
The general function of all three I/O interface boards is identical ; each board operating independently due to its own processor logic.
Each I/O interface board consists of five main logic groups:
Each of the three interface boards consists of three independent I/O (input/output) interfaces:
- the discrete I/O interfaces
- the ARINC I/O interfaces
- the serial interfaces.
The general function of all three I/O interface boards is identical ; each board operating independently due to its own processor logic.
Each I/O interface board consists of five main logic groups:
- processor logic
- discrete I/O interface logic
- ARINC I/O interface logic
- serial interface logic
- bus logic.
1 Processor logic
The following functional groups are discussed under this heading:
The following functional groups are discussed under this heading:
- Central Processing Unit (CPU)
- local data RAM, program PROM and relabelling EPROM
- address decoder and DTACK generator
- interrupt logic
- watchdog timer and reset logic
- clock generator.
a Central Processing Unit (CPU)
The CPU is a 16-bit microprocessor from the MC68020 family. It is always in one of the following three processing states:
The CPU is a 16-bit microprocessor from the MC68020 family. It is always in one of the following three processing states:
- normal processing state, which is associated with intruction execution. In this state, the CPU fetches instructions/operands from its program PROM or the COMMON RAM, processes them and stores the final result back in the COMMON RAM. (The COMMON RAM is located on the DPU1 (PFD) board)
- execution processing state, which is associated with interrupts, trap instructions and other exceptional conditions. In this case, a vector number, which is fetched from the program PROM, is fed to the CPU via the CPU-DATA-BUS. The vector number is processed in the CPU and relevant addresses are sent to fetch the necessary instruction from the program PROM. The CPU executes this instruction in order to carry out the necessary operation.
- halted processing state, which is an indication of a catastrophic hardware failure. For example, if during the exception processing of a bus-error another bus-error occurs, the CPU assumes that the system is unusable and halts.
b Local data RAM, program PROM and relabelling EPROM
When the CPU is in one of its three processing states, it requires intermediate storing facility for data/results. This is provided by the 2Kx16-bit local data RAM.
The program PROM has a total storage capacity of 8Kx16-bit words.
It contains the instructions carried out by the CPU during its normal processing state as well as the exception vectors required during the exception processing state - in short, the complete operational software required by this board is stored in the program PROM.
The relebelling EPROM has a total storage capacity of 32Kx16-bit words. The relabelled addresses for the COMMON RAM (for the data received through the ARINC I/O interface logic) as well as the test library (for the self tests) and a monitoring program for this board (for maintenance operations) are stored in the relabelling EPROM.
All three memories are addressed by the CPU-ADDRESS-BUS and data transfer takes place through the CPU-DATA-BUS. The address decoder provides the enable-signals and the CPU the read/write signals.
When the CPU is in one of its three processing states, it requires intermediate storing facility for data/results. This is provided by the 2Kx16-bit local data RAM.
The program PROM has a total storage capacity of 8Kx16-bit words.
It contains the instructions carried out by the CPU during its normal processing state as well as the exception vectors required during the exception processing state - in short, the complete operational software required by this board is stored in the program PROM.
The relebelling EPROM has a total storage capacity of 32Kx16-bit words. The relabelled addresses for the COMMON RAM (for the data received through the ARINC I/O interface logic) as well as the test library (for the self tests) and a monitoring program for this board (for maintenance operations) are stored in the relabelling EPROM.
All three memories are addressed by the CPU-ADDRESS-BUS and data transfer takes place through the CPU-DATA-BUS. The address decoder provides the enable-signals and the CPU the read/write signals.
c Address decoder and DTACK generator
The addresses generated by the CPU are decoded by the address decoder in order to deliver the required enable-signals on this board.
The DTACK generator asserts the signal DTACK* in order to inform the CPU that the CPU-DATA-BUS is being used for a data transfer.
The addresses generated by the CPU are decoded by the address decoder in order to deliver the required enable-signals on this board.
The DTACK generator asserts the signal DTACK* in order to inform the CPU that the CPU-DATA-BUS is being used for a data transfer.
d Interrupt logic
The interrupt logic has two functions:
Their priority-level is encoded by the interrupt logic via three interrupt-priority-level signals IPL0* - IPL2* sent to the CPU.
When the CPU acknowledges an interrupt-request, it asserts its function-code-outputs FC0 - FC2 and ADDRESS-STROBE signal AS* accordingly. The interrupt logic then activates either interrupt-acknowledge-signal IACK5* (MFP) or IACK4* (ACIA), which informs the RS232 or RS422 interface that an interrupt has been granted.
When data from the FMGC or FWC is received by an I/O interface board, its CPU can initiate an interrupt cycle on the DPU board. In such a case, the CPU on the I/O interface board sends relevant addresses through its CPU-ADDRESS-BUS in order to activate signals CE INT1* or CE INT2* via the address decoder. These signals are transmitted via the interrupt logic as signals IRQ1* (FWC) or IRQ2* (FMGC) to the relevant DPU board to claim an interrupt in its CPU operation.
The interrupt logic has two functions:
- initiate an interrupt in the CPU operation on the I/O interface board
- initiate an interrupt in the CPU operation on the DPU board.
Their priority-level is encoded by the interrupt logic via three interrupt-priority-level signals IPL0* - IPL2* sent to the CPU.
When the CPU acknowledges an interrupt-request, it asserts its function-code-outputs FC0 - FC2 and ADDRESS-STROBE signal AS* accordingly. The interrupt logic then activates either interrupt-acknowledge-signal IACK5* (MFP) or IACK4* (ACIA), which informs the RS232 or RS422 interface that an interrupt has been granted.
When data from the FMGC or FWC is received by an I/O interface board, its CPU can initiate an interrupt cycle on the DPU board. In such a case, the CPU on the I/O interface board sends relevant addresses through its CPU-ADDRESS-BUS in order to activate signals CE INT1* or CE INT2* via the address decoder. These signals are transmitted via the interrupt logic as signals IRQ1* (FWC) or IRQ2* (FMGC) to the relevant DPU board to claim an interrupt in its CPU operation.
NOTE: IRQ1* (FWC) is generated on I/O interface 2 board only and is transmitted to DPU2 (ND) board. IRQ2* can be generated on all three interface boards and sent to DPU3 (ECAM) board.
e Watchdog timer and reset logic
The watchdog timer continuously monitors the trigger-watch-dog-flag TRW* from the ARINC control register (in ARINC I/O interface logic) at intervals determined by a clock from the clock generator. In case the flag TRW* remains inactive for a period longer than 350 ms (which happens if an error occurs during the normal processing state of the CPU), the watchdog timer generates a watchdog-reset (WDR*) signal. This resets the CPU via the RESET logic.
When the unit is powered on or when the signal WDR* is activated by the watchdog timer, the reset logic resets the CPU.
The watchdog timer continuously monitors the trigger-watch-dog-flag TRW* from the ARINC control register (in ARINC I/O interface logic) at intervals determined by a clock from the clock generator. In case the flag TRW* remains inactive for a period longer than 350 ms (which happens if an error occurs during the normal processing state of the CPU), the watchdog timer generates a watchdog-reset (WDR*) signal. This resets the CPU via the RESET logic.
When the unit is powered on or when the signal WDR* is activated by the watchdog timer, the reset logic resets the CPU.
f Clock generator
The clock generator consists of a quartz oscillator and two frequency dividers. The quartz oscillator generates a 20 MHz clock and the frequency dividers divide this clock to output various derivative clocks, which are required on this board.
The clock generator consists of a quartz oscillator and two frequency dividers. The quartz oscillator generates a 20 MHz clock and the frequency dividers divide this clock to output various derivative clocks, which are required on this board.
2 Discrete I/O interface logic
Five functional groups are discussed under this heading:
Five functional groups are discussed under this heading:
- discrete input interface
- discrete output interface
- discrete wrap around test logic
- DMC invalid relay
- discrete decoder.
a Discrete input interface
This interface, made up of the discrete input hybrid modules and the discrete input latches, can handle a total of 20 discrete inputs (type OPEN/GND). Under the control of the CPU, the inputs are routed through the I/O-DATA-BUS, the I/O data bus coupler and the CPU-DATA-BUS to the COMMON RAM (on the DPU1 (PFD) board) for storage until further use.
The CPU activates TEST MODE and TEST HI/LO via the MFP on the board in order to test the hybrid modules and the latches in this interface.
This interface, made up of the discrete input hybrid modules and the discrete input latches, can handle a total of 20 discrete inputs (type OPEN/GND). Under the control of the CPU, the inputs are routed through the I/O-DATA-BUS, the I/O data bus coupler and the CPU-DATA-BUS to the COMMON RAM (on the DPU1 (PFD) board) for storage until further use.
The CPU activates TEST MODE and TEST HI/LO via the MFP on the board in order to test the hybrid modules and the latches in this interface.
b Discrete output interface
This interface, made up of the discrete output module and the discrete output latch, can handle 4 discrete outputs.
These outputs are fetched from the COMMON RAM, under the control of the CPU, and routed through this interface to external peripherals.
This interface, made up of the discrete output module and the discrete output latch, can handle 4 discrete outputs.
These outputs are fetched from the COMMON RAM, under the control of the CPU, and routed through this interface to external peripherals.
c Discrete wrap around test logic
This logic provides a wrap-around-test facility for the discrete I/O interface logic. The wrap-around loop is formed by the discrete output interface, a wrap around hybrid module and a wrap around latch. During the test, the CPU transmits four bits through the CPU-DATA-BUS and through this wrap-around-loop and then executes a status-check.
This logic provides a wrap-around-test facility for the discrete I/O interface logic. The wrap-around loop is formed by the discrete output interface, a wrap around hybrid module and a wrap around latch. During the test, the CPU transmits four bits through the CPU-DATA-BUS and through this wrap-around-loop and then executes a status-check.
d DMC invalid relay
This relay is mounted on the I/O interface 3 board only. When the DMC is switched on, it executes a short self-test cycle, during which the bit D01 at the output of the discrete output module is LOW. The DMC invalid relay is thereby energized and signal DMC-INVALID is OPEN : an indication that the DMC is not accessible for operation during this time. After the self-test cycle, bit D01 goes to HIGH and remains HIGH during the normal operation of the DMC. This de-energizes the relay and signal DMC-INVALID is held continuously at LOW.
In the case of an abnormal condition in the DMC, bit D01 is again set to LOW, causing the signal DMC-INVALID to become OPEN.
This relay is mounted on the I/O interface 3 board only. When the DMC is switched on, it executes a short self-test cycle, during which the bit D01 at the output of the discrete output module is LOW. The DMC invalid relay is thereby energized and signal DMC-INVALID is OPEN : an indication that the DMC is not accessible for operation during this time. After the self-test cycle, bit D01 goes to HIGH and remains HIGH during the normal operation of the DMC. This de-energizes the relay and signal DMC-INVALID is held continuously at LOW.
In the case of an abnormal condition in the DMC, bit D01 is again set to LOW, causing the signal DMC-INVALID to become OPEN.
e Discrete decoder
The addresses on the CPU-ADDRESS-BUS are decoded by this decoder in order to deliver the enable- and clock-signals for the discrete I/O interface logic.
The addresses on the CPU-ADDRESS-BUS are decoded by this decoder in order to deliver the enable- and clock-signals for the discrete I/O interface logic.
3 ARINC I/O interface logic
Four main functional groups are discussed under this heading:
Four main functional groups are discussed under this heading:
- ARINC interface modules
- ARINC decoder
- control and status registers
- ARINC latches.
a ARINC interface modules
There are nine ARINC interface modules on each I/O interface board.
Each interface module contains two receivers and one transmitter, all three operating independently. The function of the receiver is to receive serial data as per ARINC 429 specification via an input channel, convert it into 16-bit words and transmit these through the I/O-DATA-BUS, I/O data bus coupler and the CPU-DATA-BUS for relabelling purpose. The function of the transmitter is to receive 16-bit words through the CPU-DATA-BUS and I/O-DATA-BUS, convert them to serial bits and transmit these via the ARINC output driver to external devices.
Each I/O interface board can thus handle a maximum of 18 inputs (6 high-speed and 12 low-speed) and 9 outputs (only 1 output is, however, used).
There are nine ARINC interface modules on each I/O interface board.
Each interface module contains two receivers and one transmitter, all three operating independently. The function of the receiver is to receive serial data as per ARINC 429 specification via an input channel, convert it into 16-bit words and transmit these through the I/O-DATA-BUS, I/O data bus coupler and the CPU-DATA-BUS for relabelling purpose. The function of the transmitter is to receive 16-bit words through the CPU-DATA-BUS and I/O-DATA-BUS, convert them to serial bits and transmit these via the ARINC output driver to external devices.
Each I/O interface board can thus handle a maximum of 18 inputs (6 high-speed and 12 low-speed) and 9 outputs (only 1 output is, however, used).
b ARINC decoder
This decoder decodes the addresses on the CPU-ADDRESS-BUS in order to deliver the enable- and clock-signals for the ARINC I/O interface logic.
This decoder decodes the addresses on the CPU-ADDRESS-BUS in order to deliver the enable- and clock-signals for the ARINC I/O interface logic.
c Control and status registers
The CPU uses the control register to activate definite signals by setting certain bits on the CPU-DATA-BUS. It can thus:
The CPU uses the control register to activate definite signals by setting certain bits on the CPU-DATA-BUS. It can thus:
- enable the transmitter section in the ARINC interface module
- enable the ARINC output driver
- perform a general reset for certain sections of the discrete-, ARINC- and serial- I/O interface logic via signal RES I/O*
- trigger the watchdog timer via signal TRW*.
d ARINC latches
These latches inform the CPU about the status of the receiver- and transmitter-sections inside the ARINC interface modules via definite signals.
These latches inform the CPU about the status of the receiver- and transmitter-sections inside the ARINC interface modules via definite signals.
4 Serial interface logic
There are two serial interfaces on each I/O interface board :
There are two serial interfaces on each I/O interface board :
- RS422 interface
- RS232 interface.
a RS422 interface
This interface receives serial-data from an external device. It converts this data to 8-bit parallel data and loads it on the CPU-DATA-BUS for eventual storage in the COMMON RAM (on the DPU1 (PFD) in the COMMON RAM) (on the DPU1 (PFD) board).
It consists of a line receiver and an ACIA (asynchronous communications interface adapter). The line receiver renders the serial-data-input TTL compatible and feeds it to the ACIA, which in turn is responsible for the actual serial-to-parallel conversion.
This interface receives serial-data from an external device. It converts this data to 8-bit parallel data and loads it on the CPU-DATA-BUS for eventual storage in the COMMON RAM (on the DPU1 (PFD) in the COMMON RAM) (on the DPU1 (PFD) board).
It consists of a line receiver and an ACIA (asynchronous communications interface adapter). The line receiver renders the serial-data-input TTL compatible and feeds it to the ACIA, which in turn is responsible for the actual serial-to-parallel conversion.
b RS232 interface
This interface is used for maintenance purposes and provides a serial communication with an external device (e.g. debugger). It consists of a MFP (multi-function peripheral) and two line drivers.
The MFP which has more functions than those described above, is an integrated module consisting of the following functional groups :
The GPIP handles two inputs (from the power supply module) and two outputs (to the discrete I/O interface logic). The power supply module uses the GPIP for two purposes : firstly it informs the CPU on the board about the status of the signal SPID and secondly, it requests an interrupt in the CPU operation with signal POWER LOW.
The CPU uses the GPIP for only one purpose : it tests the discrete input interface (in the discrete I/O interface logic) with signals TEST MODE and TEST HI/LO.
The interrupt controller handles interrupt-requests for an interrupt in the CPU operation received via the GPIP as well as those generated internally in the MFP by the UART. It sets priority-levels for these requests and sends signal IRQ5* (MFP) to the interrupt logic. When the request is granted by the CPU, it receives the signal IACK5* (MFP).
The timers A and B are cascaded and operate as a real time counter, whereas the timers C and D provide the baud-rate clocks for the ACIA in the serial interface logic and the UART in this MFP.
The UART (universal asynchronous receiver transmitter) in the MFP, as already explained, provides asynchronous serial communication with an external device (e.g. debugger) via the line drivers during maintenance operations. To accomplish this task, the UART operates in the receiver or in the transmitter mode.
This interface is used for maintenance purposes and provides a serial communication with an external device (e.g. debugger). It consists of a MFP (multi-function peripheral) and two line drivers.
The MFP which has more functions than those described above, is an integrated module consisting of the following functional groups :
- general purpose I/O port (GPIP)
- interrupt controller
- timers A, B and C, D
- UART.
The GPIP handles two inputs (from the power supply module) and two outputs (to the discrete I/O interface logic). The power supply module uses the GPIP for two purposes : firstly it informs the CPU on the board about the status of the signal SPID and secondly, it requests an interrupt in the CPU operation with signal POWER LOW.
The CPU uses the GPIP for only one purpose : it tests the discrete input interface (in the discrete I/O interface logic) with signals TEST MODE and TEST HI/LO.
The interrupt controller handles interrupt-requests for an interrupt in the CPU operation received via the GPIP as well as those generated internally in the MFP by the UART. It sets priority-levels for these requests and sends signal IRQ5* (MFP) to the interrupt logic. When the request is granted by the CPU, it receives the signal IACK5* (MFP).
The timers A and B are cascaded and operate as a real time counter, whereas the timers C and D provide the baud-rate clocks for the ACIA in the serial interface logic and the UART in this MFP.
The UART (universal asynchronous receiver transmitter) in the MFP, as already explained, provides asynchronous serial communication with an external device (e.g. debugger) via the line drivers during maintenance operations. To accomplish this task, the UART operates in the receiver or in the transmitter mode.
5 Bus logic
The following functional groups are discussed under this heading :
The following functional groups are discussed under this heading :
- bus request logic
- bus time out logic
- bus couplers.
a Bus request logic
The bus request logic is integrated into a 20-pin gate array module. The gate array also contains the bus time out logic (discussed in this chapter) and the reset logic (discussed under processor logic).
The bus request logic consists internally of a bus requester and a bus master control.
When the CPU on any I/O interface board wants access to the COMMON BUS, it activates signal CE BUS* via the address decoder (in the processor logic). The bus requester recognizes this signal CE BUS* and sends the bus-request signal BR* to the bus arbiter (on DPU1 (PFD) board). When the request is granted by this bus arbiter, it asserts a bus-grant input-signal BG IN*.
Access to the COMMON BUS by any one of the three I/O interface boards is based on priority rules i.e. I/O interface 1 board has the lowest priority among the three boards.
Once the bus-grant has been accepted by a bus requester, it sends signal BUSY* to the bus arbiter to indicate that the bus is now being used by its CPU. Signals CE STATUS* (from the address decoder) and bit D15 (on CPU-DATA-BUS) are activated when the CPU claims access to the COMMON BUS. These two signals ensure that signal BUSY* is held in active state as long as communication with the COMMON RAM or BITE memory (both on DPU1 (PFD) board) continues. When the CPU no longer requires the COMMON BUS, it activates ADDRESS-STROBE signal AS* and signal BUSY* becomes inactive.
The function of the bus master control in the gate array is to generate enable-signals for the bus couplers once access to the COMMON BUS has been attained, so that an information transfer between the local buses on the I/O interface board and the COMMON BUS can take place. The enable-signal EN ADDA* enables the local data and address bus couplers, whereas enable-signal ENS* enables the local control bus coupler. The bus master control is clocked by XCK68K from the clock generator and the bus-acknowledge signal BACK remains HIGH as long as the information transfer takes place.
All output signals from the bus requester and the bus master control are reset when the reset logic, also in the gate array is initiated.
The bus request logic is integrated into a 20-pin gate array module. The gate array also contains the bus time out logic (discussed in this chapter) and the reset logic (discussed under processor logic).
The bus request logic consists internally of a bus requester and a bus master control.
When the CPU on any I/O interface board wants access to the COMMON BUS, it activates signal CE BUS* via the address decoder (in the processor logic). The bus requester recognizes this signal CE BUS* and sends the bus-request signal BR* to the bus arbiter (on DPU1 (PFD) board). When the request is granted by this bus arbiter, it asserts a bus-grant input-signal BG IN*.
Access to the COMMON BUS by any one of the three I/O interface boards is based on priority rules i.e. I/O interface 1 board has the lowest priority among the three boards.
Once the bus-grant has been accepted by a bus requester, it sends signal BUSY* to the bus arbiter to indicate that the bus is now being used by its CPU. Signals CE STATUS* (from the address decoder) and bit D15 (on CPU-DATA-BUS) are activated when the CPU claims access to the COMMON BUS. These two signals ensure that signal BUSY* is held in active state as long as communication with the COMMON RAM or BITE memory (both on DPU1 (PFD) board) continues. When the CPU no longer requires the COMMON BUS, it activates ADDRESS-STROBE signal AS* and signal BUSY* becomes inactive.
The function of the bus master control in the gate array is to generate enable-signals for the bus couplers once access to the COMMON BUS has been attained, so that an information transfer between the local buses on the I/O interface board and the COMMON BUS can take place. The enable-signal EN ADDA* enables the local data and address bus couplers, whereas enable-signal ENS* enables the local control bus coupler. The bus master control is clocked by XCK68K from the clock generator and the bus-acknowledge signal BACK remains HIGH as long as the information transfer takes place.
All output signals from the bus requester and the bus master control are reset when the reset logic, also in the gate array is initiated.
b Bus time out logic
The bus time out logic is also integrated into the 20-pin gate array module. It determines how long the CPU can claim access to the COMMON BUS. The time interval begins with signals CE BUS* and BACK going active i.e. when the CPU has attained access to the COMMON BUS, whereas the timing is monitored by clock XCK68K from the clock generator. On completion of the specified time interval, signal BERR* is activated in order to stop the CPU. This signal can also be activated when the reset logic, also in gate array, is initiated.
The bus time out logic is also integrated into the 20-pin gate array module. It determines how long the CPU can claim access to the COMMON BUS. The time interval begins with signals CE BUS* and BACK going active i.e. when the CPU has attained access to the COMMON BUS, whereas the timing is monitored by clock XCK68K from the clock generator. On completion of the specified time interval, signal BERR* is activated in order to stop the CPU. This signal can also be activated when the reset logic, also in gate array, is initiated.
c Bus couplers
There are three types of bus couplers on each I/O interface board - the local data bus coupler, the local address bus coupler and the local control bus coupler and the local control bus coupler.
The local data bus coupler consists of two bi-directional line drivers. They enable data transfer between the CPU-DATA-BUS (D00-D15) on each I/O interface board and the COMMON-DATA-BUS (BD00-BD15). They are enabled by the enable-signal EN ADDA*, which is generated by the bus master control when the I/O interface board has been granted access to the COMMON BUS. The direction of the line drivers is determined by signal R/W* from the CPU.
The local address bus coupler consists of two uni-directional line drivers. When enabled by signal EN ADDA* (active LOW), they tranfer addresses, generated by the CPU from its CPU-ADDRESS-BUS (A00-A16) to the COMMON-ADDRESS-BUS (BA01-BA16).
The local control bus coupler enables a bi-directional transfer of control signals between the I/O interface board and the DPU1 (PFD) board (common RAM and BITE memory only) via the COMMON-CONTROL-BUS.
There are three types of bus couplers on each I/O interface board - the local data bus coupler, the local address bus coupler and the local control bus coupler and the local control bus coupler.
The local data bus coupler consists of two bi-directional line drivers. They enable data transfer between the CPU-DATA-BUS (D00-D15) on each I/O interface board and the COMMON-DATA-BUS (BD00-BD15). They are enabled by the enable-signal EN ADDA*, which is generated by the bus master control when the I/O interface board has been granted access to the COMMON BUS. The direction of the line drivers is determined by signal R/W* from the CPU.
The local address bus coupler consists of two uni-directional line drivers. When enabled by signal EN ADDA* (active LOW), they tranfer addresses, generated by the CPU from its CPU-ADDRESS-BUS (A00-A16) to the COMMON-ADDRESS-BUS (BA01-BA16).
The local control bus coupler enables a bi-directional transfer of control signals between the I/O interface board and the DPU1 (PFD) board (common RAM and BITE memory only) via the COMMON-CONTROL-BUS.
(c) WXR board
The echoes of 800 beams are received by the WRX antenna every half revolution (4 s.). Each beam echo contains 512 separate signals corresponding to the strength of the beam reflection at 512 separate points in the airspace in front of the aircraft.
The strength of the reflection at each point is converted into a 3 bit code (1 BIN), which is the color mode for that particular point. This information is transmitted serially via an ARINC input channel to the WXR board, i.e. at any given time, 512 x 3 = 1536 serial bits or 512 BINs, which represent the color information of one beam, are received by the WXR board. In addition to the BIN information, the WXR board also receives four control words of 16 bits each as well as two signals, START SYNC and END SYNC, of approximately 3 bits each. The signal START SYNC heralds the start of the input word and signal END SYNC its end. The four control words are fetched by the DPU2 (ND) board and the BIN information is processed directly on this board.
The WXR board can be sub-divided into the following main functional blocks:
The echoes of 800 beams are received by the WRX antenna every half revolution (4 s.). Each beam echo contains 512 separate signals corresponding to the strength of the beam reflection at 512 separate points in the airspace in front of the aircraft.
The strength of the reflection at each point is converted into a 3 bit code (1 BIN), which is the color mode for that particular point. This information is transmitted serially via an ARINC input channel to the WXR board, i.e. at any given time, 512 x 3 = 1536 serial bits or 512 BINs, which represent the color information of one beam, are received by the WXR board. In addition to the BIN information, the WXR board also receives four control words of 16 bits each as well as two signals, START SYNC and END SYNC, of approximately 3 bits each. The signal START SYNC heralds the start of the input word and signal END SYNC its end. The four control words are fetched by the DPU2 (ND) board and the BIN information is processed directly on this board.
The WXR board can be sub-divided into the following main functional blocks:
- ARINC 708 interface and manchester decoder
- beam shift register and file register
- beam buffer
- main memory
- output circuitry.
1 ARINC 708 interface and manchester decoder
Four input channels feed WXR serial input words to the ARINC 708 interface. All inputs are in manchester bi-phase code ; the bit-rate in each word being 1 MHz. Only one channel is selected for processing by the signal CHANNEL SEL, activated by the DPU2 (ND) board via word register 5. The manchester bits in the serial input words are transformed to TTL voltage levels by this interface and fed via a MUX to the manchester decoder.
During a test operation of the WXR board, the DPU2 (ND) board activates the signal TEST ON in word register 6, which switches the MUX to select a simulated beam from the test pattern generation logic and sends it to the manchester decoder.
The manchester decoder is responsible for determining the beginning and the end of each serial input word received from the ARINC 708 interface and converting the input bits to NRZ (non-return to zero) bits. It consists of a shift register, a latch and a bit detection PROM. The serial data input is continuously sampled at 8 MHz, i.e., each input bit is sampled 8 times, out of which the first and last samples are disregarded. The sample result is latched and forms the address to the bit detection PROM. When the PROM receives the 3 sequential addresses denoted by START SYNC, it is conditioned to decode the subsequent data bits into NRZ code.
Each bit in the four control words as well as in the following BIN information is converted from a manchester-bit to a NRZ-bit. When the bit detection PROM receives the 3 sequential addresses denoted by END SYNC, this indicates that a complete valid beam information has been decoded by the manchester decoder.
It will be noted that, after the START SYNC has been detected, the LOOP address is 011. Under this condition all following data bits are converted to NRZ. A change-over from LOW to HIGH in the input data bit corresponds to a LOW NRZ-bit, whereas a change-over from HIGH to LOW in the input data bit corresponds to a HIGH NRZ bit.
Four input channels feed WXR serial input words to the ARINC 708 interface. All inputs are in manchester bi-phase code ; the bit-rate in each word being 1 MHz. Only one channel is selected for processing by the signal CHANNEL SEL, activated by the DPU2 (ND) board via word register 5. The manchester bits in the serial input words are transformed to TTL voltage levels by this interface and fed via a MUX to the manchester decoder.
During a test operation of the WXR board, the DPU2 (ND) board activates the signal TEST ON in word register 6, which switches the MUX to select a simulated beam from the test pattern generation logic and sends it to the manchester decoder.
The manchester decoder is responsible for determining the beginning and the end of each serial input word received from the ARINC 708 interface and converting the input bits to NRZ (non-return to zero) bits. It consists of a shift register, a latch and a bit detection PROM. The serial data input is continuously sampled at 8 MHz, i.e., each input bit is sampled 8 times, out of which the first and last samples are disregarded. The sample result is latched and forms the address to the bit detection PROM. When the PROM receives the 3 sequential addresses denoted by START SYNC, it is conditioned to decode the subsequent data bits into NRZ code.
Each bit in the four control words as well as in the following BIN information is converted from a manchester-bit to a NRZ-bit. When the bit detection PROM receives the 3 sequential addresses denoted by END SYNC, this indicates that a complete valid beam information has been decoded by the manchester decoder.
It will be noted that, after the START SYNC has been detected, the LOOP address is 011. Under this condition all following data bits are converted to NRZ. A change-over from LOW to HIGH in the input data bit corresponds to a LOW NRZ-bit, whereas a change-over from HIGH to LOW in the input data bit corresponds to a HIGH NRZ bit.
2 Beam shift register and file register
After the signal START SYNC has been detected in the input word, the manchester decoder outputs the first 16 NRZ bits of the first control word. These 16 NRZ bits are shifted serially into the beam shift register, under the control of the beam control logic. In order to load these 16-bits into the file register, the beam control logic provides the write-enable signal, whereas the control word counter determines the location of the bits in the file register. In this way all four control words from an input word are eventually stored in the file register. The beam control logic now generates an interrupt, which is transmitted to the DPU2 (ND) board. The interrupt-routine enables the DPU2 (ND) board to fetch the four control words via the bus couplers (slave) and process them. The scan angle of the beam, contained in control word 4, is added to the drift angle on the DPU2 (ND) board and the result - the computed angle - is fed back to the WXR board (COMP. ANGLE at word register 5).
After the signal START SYNC has been detected in the input word, the manchester decoder outputs the first 16 NRZ bits of the first control word. These 16 NRZ bits are shifted serially into the beam shift register, under the control of the beam control logic. In order to load these 16-bits into the file register, the beam control logic provides the write-enable signal, whereas the control word counter determines the location of the bits in the file register. In this way all four control words from an input word are eventually stored in the file register. The beam control logic now generates an interrupt, which is transmitted to the DPU2 (ND) board. The interrupt-routine enables the DPU2 (ND) board to fetch the four control words via the bus couplers (slave) and process them. The scan angle of the beam, contained in control word 4, is added to the drift angle on the DPU2 (ND) board and the result - the computed angle - is fed back to the WXR board (COMP. ANGLE at word register 5).
3 Beam buffer
After the four control words have been loaded into the file register, the first BIN (3 bits) in the input word is shifted serially into the beam shift register, under the control of the beam control logic.
In order to load the BIN in the beam buffer, the beam control logic provides the write-enable signal and the BIN counter determines the location of the BIN in the beam buffer. The beam buffer is a RAM with a total storage capacity if 1K x 4-bit (only 1K x 3-bit used).
In this way, all 512 BINs are eventually transferred to the beam buffer and at any given time, the beam buffer contains the complete color information (512 BINs) of one beam).
When the signal END SYNC at the end of the input word is recognized, the beam control logic initiates a read-operation of the beam buffer.
During this operation, a BIN (3 bits) is read out and presented to the main memory via four hex line drivers. The three bits in each BIN read out of the beam buffer are fanned out by the hex line drivers so that the main memory, which consists of four modules, receives a total of twelve data-bits ; each module receiving three bits (one BIN). This ensures that all four modules in the main memory are presented with identical BIN information.
After the four control words have been loaded into the file register, the first BIN (3 bits) in the input word is shifted serially into the beam shift register, under the control of the beam control logic.
In order to load the BIN in the beam buffer, the beam control logic provides the write-enable signal and the BIN counter determines the location of the BIN in the beam buffer. The beam buffer is a RAM with a total storage capacity if 1K x 4-bit (only 1K x 3-bit used).
In this way, all 512 BINs are eventually transferred to the beam buffer and at any given time, the beam buffer contains the complete color information (512 BINs) of one beam).
When the signal END SYNC at the end of the input word is recognized, the beam control logic initiates a read-operation of the beam buffer.
During this operation, a BIN (3 bits) is read out and presented to the main memory via four hex line drivers. The three bits in each BIN read out of the beam buffer are fanned out by the hex line drivers so that the main memory, which consists of four modules, receives a total of twelve data-bits ; each module receiving three bits (one BIN). This ensures that all four modules in the main memory are presented with identical BIN information.
4 Main memory
The main memory consists of four 16K x 4 bit dynamic RAMs (only 16K x 3 bit used) ; it thus has a total storage capacity of 64K x 4 bit (only 64K x 3 bit used). All four RAMs are presented with identical data from the beam buffer and have identical addresses at their address-inputs via the MAIN-MEMORY-ADDRESS-BUS. The selection of a particular RAM for the write-operation is, however, done by the signals W1* to W4* from the main memory control logic : whereas during the read-operation, all four RAMs are read simultaneously.
The area on the ND (Navigation Display), where the WXR map is to be drawn, consists of a 256 x 256 grid point array ; each point being defined by an X- and Y- coordinate. The contents of the main memory are analogous to this grid, where each grid point is a memory location.
The main memory write logic (X- and Y-address counters) determines the location of each BIN in the main memory during the write-operation. In order to do this, it delivers row-addresses and column-addresses via the MAIN-MEMORY-BUS. When one of the signals W1* to W4* goes to LOW, a BIN is written in a particular RAM. The X- and Y-address counters in this logic are activated by the X/Y incrementation logic via the main memory control logic.
The main memory read logic (X- and Y-address counters) provides the row-addresses and column-addresses via the MAIN-MEMORY-ADDRESS-BUS during the read-operation in the main memory. As all RAMs are addressed and enabled simultaneously, 4 BINs (12 bits) are thus read out from the main memory and transmitted through the MAIN-MEMORY-DATA-BUS. Reading out of the main memory is executed using the meander-scan techniques. The X-address counters in this logic are thus conditioned for up-counting only, whereas the Y-address counters are conditioned for up- and down-counting alternately.
There are two comparators - X and Y. The Y-comparator compares the position of the Y-address counter with the upper and lower limits of a writing mask fixed by the DPU2 (ND) board - ENDP.Y and START.Y.
On reaching these limits, the Y-address counter begins its down- or up-count accordingly. The X-comparator compares the position of the X-address counter with the extreme-right limit of the writing-mask (ENDP.X). When these two parameters match, the X-comparator activates the signal X LIMIT*, which, in turn, asserts signal END OF WXR* in order to inform the DPU2 (ND) board that a complete beam has been read out of the main memory i.e. the beam has been simultaneously drawn on the ND.
The 800 beams, which are received and processed by the WXR board every 4 s. to draw a WXR map on the ND, do not necessarily contain all the information for a complete picture. This is especially true, as the beams diverge at greater ranges. In order to provide color information to all BINs from which the WXR map is formed, a "slave beam is generated immediately after each master beam.
In order to achieve this, the beam buffer is read twice. By the first read out, the BIN information of a beam is read out, as already explained, from the beam buffer (the BIN information is, thereby, not erased) and written into the main memory, the addresses of which are calculated by the main memory write logic from the COMP. ANGLE (calculated on the DPU2 (ND) board) of the main beam ; by the second read out, the same BIN information is read out once again from the beam buffer and written into the main memory under new addresses.
These addresses are calculated by the main memory write logic from the same COMP. ANGLE plus Delta x and Delta y respectively from the X/Y incrementation logics ; Delta x and Delta y being fixed values delivered under control of main memory control logic. This way, each time a slave beam is written into the main memory immediately after the master beam. Correspondingly, the master beam is read out from the main memory followed by the slave beam.
The main memory consists of four 16K x 4 bit dynamic RAMs (only 16K x 3 bit used) ; it thus has a total storage capacity of 64K x 4 bit (only 64K x 3 bit used). All four RAMs are presented with identical data from the beam buffer and have identical addresses at their address-inputs via the MAIN-MEMORY-ADDRESS-BUS. The selection of a particular RAM for the write-operation is, however, done by the signals W1* to W4* from the main memory control logic : whereas during the read-operation, all four RAMs are read simultaneously.
The area on the ND (Navigation Display), where the WXR map is to be drawn, consists of a 256 x 256 grid point array ; each point being defined by an X- and Y- coordinate. The contents of the main memory are analogous to this grid, where each grid point is a memory location.
The main memory write logic (X- and Y-address counters) determines the location of each BIN in the main memory during the write-operation. In order to do this, it delivers row-addresses and column-addresses via the MAIN-MEMORY-BUS. When one of the signals W1* to W4* goes to LOW, a BIN is written in a particular RAM. The X- and Y-address counters in this logic are activated by the X/Y incrementation logic via the main memory control logic.
The main memory read logic (X- and Y-address counters) provides the row-addresses and column-addresses via the MAIN-MEMORY-ADDRESS-BUS during the read-operation in the main memory. As all RAMs are addressed and enabled simultaneously, 4 BINs (12 bits) are thus read out from the main memory and transmitted through the MAIN-MEMORY-DATA-BUS. Reading out of the main memory is executed using the meander-scan techniques. The X-address counters in this logic are thus conditioned for up-counting only, whereas the Y-address counters are conditioned for up- and down-counting alternately.
There are two comparators - X and Y. The Y-comparator compares the position of the Y-address counter with the upper and lower limits of a writing mask fixed by the DPU2 (ND) board - ENDP.Y and START.Y.
On reaching these limits, the Y-address counter begins its down- or up-count accordingly. The X-comparator compares the position of the X-address counter with the extreme-right limit of the writing-mask (ENDP.X). When these two parameters match, the X-comparator activates the signal X LIMIT*, which, in turn, asserts signal END OF WXR* in order to inform the DPU2 (ND) board that a complete beam has been read out of the main memory i.e. the beam has been simultaneously drawn on the ND.
The 800 beams, which are received and processed by the WXR board every 4 s. to draw a WXR map on the ND, do not necessarily contain all the information for a complete picture. This is especially true, as the beams diverge at greater ranges. In order to provide color information to all BINs from which the WXR map is formed, a "slave beam is generated immediately after each master beam.
In order to achieve this, the beam buffer is read twice. By the first read out, the BIN information of a beam is read out, as already explained, from the beam buffer (the BIN information is, thereby, not erased) and written into the main memory, the addresses of which are calculated by the main memory write logic from the COMP. ANGLE (calculated on the DPU2 (ND) board) of the main beam ; by the second read out, the same BIN information is read out once again from the beam buffer and written into the main memory under new addresses.
These addresses are calculated by the main memory write logic from the same COMP. ANGLE plus Delta x and Delta y respectively from the X/Y incrementation logics ; Delta x and Delta y being fixed values delivered under control of main memory control logic. This way, each time a slave beam is written into the main memory immediately after the master beam. Correspondingly, the master beam is read out from the main memory followed by the slave beam.
5 X/Y incrementation logic
The scan angle of the beam, contained in control word 4 in the input word, is added to the drift angle on the DPU2 (ND) board and the result - COMP. ANGLE - is fed back to the WXR board.
This angle is in polar coordinates and the task of this logic is to convert the polar coordinates to cartesian coordinates. It consists of sin/cos PROMs, an adder and registers where the conversion takes place. It activates the main memory write logic (X- and Y-address counters) via the main memory control logic in order to generate the required addresses for the main memory during the write-operation.
The scan angle of the beam, contained in control word 4 in the input word, is added to the drift angle on the DPU2 (ND) board and the result - COMP. ANGLE - is fed back to the WXR board.
This angle is in polar coordinates and the task of this logic is to convert the polar coordinates to cartesian coordinates. It consists of sin/cos PROMs, an adder and registers where the conversion takes place. It activates the main memory write logic (X- and Y-address counters) via the main memory control logic in order to generate the required addresses for the main memory during the write-operation.
6 Registers, WXR color code PROM and switching circuit
These three circuitries transfer the information from the main memory to the ND.
The 4 BINs (12 bits) read of the four RAMs in the main memory are latched into a register in such a way, so that it can output three groups of 4 bits each ; where each group contains a bit from a BIN.
The bits in each group are parallel-loaded into three shift registers, where a shift-right or shift-left takes place, depending on the signal UP/DOWN from the main memory read and refresh logic.
Thus, at any given time, either the three outputs (i.e. a BIN) at QA or at QD of the shift register will address the WXR color code PROM.
The WXR color code PROM contains eight color information for the BINs. It decodes the bits from the shift register and outputs three bits which determine the color of a grid point on the ND screen. This digital data (WXR COLOR) is transmitted via the driver and the switching circuit to the ND. In order to synchronize the start of this color-information-transmission with the start of the meander-scanning of the ND, a signal FRAME SYNC is coded in the color information to the ND.
The switching circuit consists of relay units. During normal operation, the relay units transfer WXR information processed on this board to the ND. In case of a breakdown of this board or this DMC, the WXR information is processed in the back-up DMC3 and the switching circuit of the failed DMC transfers the output of the WXR board in the back-up DMC3 to the ND.
These three circuitries transfer the information from the main memory to the ND.
The 4 BINs (12 bits) read of the four RAMs in the main memory are latched into a register in such a way, so that it can output three groups of 4 bits each ; where each group contains a bit from a BIN.
The bits in each group are parallel-loaded into three shift registers, where a shift-right or shift-left takes place, depending on the signal UP/DOWN from the main memory read and refresh logic.
Thus, at any given time, either the three outputs (i.e. a BIN) at QA or at QD of the shift register will address the WXR color code PROM.
The WXR color code PROM contains eight color information for the BINs. It decodes the bits from the shift register and outputs three bits which determine the color of a grid point on the ND screen. This digital data (WXR COLOR) is transmitted via the driver and the switching circuit to the ND. In order to synchronize the start of this color-information-transmission with the start of the meander-scanning of the ND, a signal FRAME SYNC is coded in the color information to the ND.
The switching circuit consists of relay units. During normal operation, the relay units transfer WXR information processed on this board to the ND. In case of a breakdown of this board or this DMC, the WXR information is processed in the back-up DMC3 and the switching circuit of the failed DMC transfers the output of the WXR board in the back-up DMC3 to the ND.
7 Delay counter, frame sync counter and line delay counter
At the beginning of the WXR ON = HIGH phase i.e. just before the actual main memory read-operation, the delay counter generates a definite delay-period after which it enables the frame sync counter.
During this delay-period, the DPU2 (ND) board informs the ND that it will be receiving color-information for BINs from the WXR board.
The frame sync counter is basically responsible to activate a synchronizing signal, which can synchronize the start of color-information-transmission from this board with the start of meander-scanning of the ND.
The main-memory, as already explained, is read using meander-scanning techniques. Thus, when the Y-address counter in the main memory read logic reaches the upper or lower limit of the writing mask, the X-address counter is enabled in order to increment its count by 1.
In order to do this, the line delay counter provides the required signal.
At the beginning of the WXR ON = HIGH phase i.e. just before the actual main memory read-operation, the delay counter generates a definite delay-period after which it enables the frame sync counter.
During this delay-period, the DPU2 (ND) board informs the ND that it will be receiving color-information for BINs from the WXR board.
The frame sync counter is basically responsible to activate a synchronizing signal, which can synchronize the start of color-information-transmission from this board with the start of meander-scanning of the ND.
The main-memory, as already explained, is read using meander-scanning techniques. Thus, when the Y-address counter in the main memory read logic reaches the upper or lower limit of the writing mask, the X-address counter is enabled in order to increment its count by 1.
In order to do this, the line delay counter provides the required signal.
8 Bus couplers, address decoder and word register
There are three types of bus couplers on this board : data bus coupler, address bus coupler and control bus coupler. The data bus coupler is bidirectional and enables a data transfer between the LOCAL-DATA-BUS and the COMMON-DATA-BUS. Its direction is determined by the DPU2 (ND) board via the control bus coupler. The address bus coupler is uni-directional and transfers the addresses received through the COMMON-ADDRESS-BUS to the address decoder. The control bus coupler transfers control signals from the DPU2 (ND) board to the address decoder on the board.
The address decoder consists of a line decoder and a PAL. Depending on whether a read- or write-operation is being executed through the COMMON-DATA-BUS, the line decoder transmits relevant control signals by decoding the address bits received via the address bus coupler.
When complete valid data is received by this board via the COMMON-DATA-BUS, the PAL sends a data-acknowledge signal to the DPU2 (ND) board. It also sends enable-signals for the line decoder and the data bus coupler.
There are a total of six word registers on this board:
There are three types of bus couplers on this board : data bus coupler, address bus coupler and control bus coupler. The data bus coupler is bidirectional and enables a data transfer between the LOCAL-DATA-BUS and the COMMON-DATA-BUS. Its direction is determined by the DPU2 (ND) board via the control bus coupler. The address bus coupler is uni-directional and transfers the addresses received through the COMMON-ADDRESS-BUS to the address decoder. The control bus coupler transfers control signals from the DPU2 (ND) board to the address decoder on the board.
The address decoder consists of a line decoder and a PAL. Depending on whether a read- or write-operation is being executed through the COMMON-DATA-BUS, the line decoder transmits relevant control signals by decoding the address bits received via the address bus coupler.
When complete valid data is received by this board via the COMMON-DATA-BUS, the PAL sends a data-acknowledge signal to the DPU2 (ND) board. It also sends enable-signals for the line decoder and the data bus coupler.
There are a total of six word registers on this board:
- two of which offer a buffer stage for information (status words) from this board to be transmitted to the DPU2 (ND) board through the COMMON-DATA-BUS
- four of which offer a buffer stage for information (control words) transmitted by the DPU2 (ND) board through the COMMON-DATA-BUS to this board.
9 Test logic
This logic helps to test the WXR board. For this, the DPU2 (ND) board generates a test beam, which is fed to the WXR board. The test beam contains 1600 bits - 64 of which represent four control words and 1536 represent the BIN information. The WXR board processes the test beam like a normal WXR beam - it transmits the first 64 bits back to the DPU2 (ND) board and stores the BIN information in the main memory. The information read out of the main memory is compared to a set information transmitted by the DPU2 (ND) board and if these match, a test counter is incremented. The test counter output is monitored by the DPU2 (ND) board and if it reaches 256 in the prescribed period, the WXR board test is positive. During the test period, an exchange of control- and status-words takes place between the DPU2 (ND) board and the WXR board - the control words set definite signals to definite levels on the WXR board, where as the status words are checked by the DPU2 (ND) board for validity.
This logic helps to test the WXR board. For this, the DPU2 (ND) board generates a test beam, which is fed to the WXR board. The test beam contains 1600 bits - 64 of which represent four control words and 1536 represent the BIN information. The WXR board processes the test beam like a normal WXR beam - it transmits the first 64 bits back to the DPU2 (ND) board and stores the BIN information in the main memory. The information read out of the main memory is compared to a set information transmitted by the DPU2 (ND) board and if these match, a test counter is incremented. The test counter output is monitored by the DPU2 (ND) board and if it reaches 256 in the prescribed period, the WXR board test is positive. During the test period, an exchange of control- and status-words takes place between the DPU2 (ND) board and the WXR board - the control words set definite signals to definite levels on the WXR board, where as the status words are checked by the DPU2 (ND) board for validity.
(d) Power supply module
The power supply module holds the following boards:
The A/C power supply 115 V/400 Hz is filtered and full-wave rectified.
This rectified voltage Vin is applied to the boost switching regulator, which consists basically of a MOSFET T1, a power inductor L, a diode D2 and filter capacitors C1, C2. When the MOSFET T1 is switched on, under control of the boost controller, the voltage Vin is applied directly across the power inductor L. Energy is thus transferred from the input supply to the power inductor. When the MOSFET T1 is turned off by the boost controller, the energy stored in the power inductor induces a voltage such that the diode D2 conducts and transfers this energy to the half bridge circuit. The voltage Vout developed in this way by the boost switching regulator is considerably higher than its input voltage Vin.
The half bridge circuit operates as a high frequency switcher and delivers high output power to the output transformer. It is controlled by the half bridge controller, which transmits pulses with variable pulse-widths.
The AC voltages transformed by the output transformer are rectified, filtered and regulated by the output voltage generators in order to supply the various DC voltages.
The power supply module holds the following boards:
- regulator/generator board
- controller/monitor board
- filter board.
The A/C power supply 115 V/400 Hz is filtered and full-wave rectified.
This rectified voltage Vin is applied to the boost switching regulator, which consists basically of a MOSFET T1, a power inductor L, a diode D2 and filter capacitors C1, C2. When the MOSFET T1 is switched on, under control of the boost controller, the voltage Vin is applied directly across the power inductor L. Energy is thus transferred from the input supply to the power inductor. When the MOSFET T1 is turned off by the boost controller, the energy stored in the power inductor induces a voltage such that the diode D2 conducts and transfers this energy to the half bridge circuit. The voltage Vout developed in this way by the boost switching regulator is considerably higher than its input voltage Vin.
The half bridge circuit operates as a high frequency switcher and delivers high output power to the output transformer. It is controlled by the half bridge controller, which transmits pulses with variable pulse-widths.
The AC voltages transformed by the output transformer are rectified, filtered and regulated by the output voltage generators in order to supply the various DC voltages.
B. CRT
(1) Cathode Ray Tube assembly
The CRT assembly is located in the central part of the DU structure.
The CRT is a Shadow-Mask color CRT potted with resin and surrounded by a metal shield. The CRT is equipped with flying leads ended by a connector, VHV lead and two photo-resistor cells.
The CRT assembly is located in the central part of the DU structure.
The CRT is a Shadow-Mask color CRT potted with resin and surrounded by a metal shield. The CRT is equipped with flying leads ended by a connector, VHV lead and two photo-resistor cells.
(2) VHV power supply
The VHV Power Supply is located on the lower part of the display unit.
It provides all the voltages required by the CRT : anode G4, focusing electrode G3, preacceleration anode G2. It also includes the control input (VHV INH) and a test output. A defocusing circuit controls the focusing electrode. It is able to thicken the electron beam for the drawing of coloured areas.
The VHV Power Supply is located on the lower part of the display unit.
It provides all the voltages required by the CRT : anode G4, focusing electrode G3, preacceleration anode G2. It also includes the control input (VHV INH) and a test output. A defocusing circuit controls the focusing electrode. It is able to thicken the electron beam for the drawing of coloured areas.
(3) Analog board
The analog board consists of the main following functions :
The analog board consists of the main following functions :
- cathode amplifiers and gamma correction
- brightness control
- G1 control (grid inhibition)
- deflection and convergence amplifiers and corrections
- monitoring, protection and orbiting circuits.
(a) Cathode amplifiers and gamma correction
1 Gamma correction
The CRT has a non-linear relationship between the beam current and the cathode voltage.
The beam current versus cathode voltage characteristics curve IK = f(VGK), for each gun must be linearized in order to compensate for this function. This is achieved by an inverse mathematical function which compensates for the curve inflection due to the CRT characteristics. Correction is provided by a circuit which generates a modulation current proportional to VGK.
The CRT has a non-linear relationship between the beam current and the cathode voltage.
The beam current versus cathode voltage characteristics curve IK = f(VGK), for each gun must be linearized in order to compensate for this function. This is achieved by an inverse mathematical function which compensates for the curve inflection due to the CRT characteristics. Correction is provided by a circuit which generates a modulation current proportional to VGK.
2 Cathode amplifier
Each cathode of the CRT to which is applied the chrominance/luminance signal is driven by a voltage.
The modulation current available on the output of the gamma correction circuit, is converted to the voltage VGK.
The conversion is performed by three hybrid cathode amplifiers (one per gun).
These amplifiers are driven by the output current from the gamma correction circuit. The cathode modulation voltage is generated from the modulation current by means of the cathode amplifier feed-back circuit.
Each cathode of the CRT to which is applied the chrominance/luminance signal is driven by a voltage.
The modulation current available on the output of the gamma correction circuit, is converted to the voltage VGK.
The conversion is performed by three hybrid cathode amplifiers (one per gun).
These amplifiers are driven by the output current from the gamma correction circuit. The cathode modulation voltage is generated from the modulation current by means of the cathode amplifier feed-back circuit.
(b) Brightness control
Correct picture display requires brightness control because of the changing environmental lighting conditions in the cockpit, and the different drawing speeds for the stroke written symbology and for the background colored areas. A first correction is made manually with the brightness potentiometer which enables the crew to adjust the general brightness level.
A second correction is performed automatically according to the environmental lighting.
The environmental lighting is measured on the front panel of the display unit by two light sensors, which provide a voltage proportional to the received lighting flux.
The brightness modulating the electronic beam takes simultaneously into account these controls and corrections.
During test of the red gun, the brightness control is replaced by a fixed voltage.
To provide these capabilities, the brightness control circuit is organized as follows :
Correct picture display requires brightness control because of the changing environmental lighting conditions in the cockpit, and the different drawing speeds for the stroke written symbology and for the background colored areas. A first correction is made manually with the brightness potentiometer which enables the crew to adjust the general brightness level.
A second correction is performed automatically according to the environmental lighting.
The environmental lighting is measured on the front panel of the display unit by two light sensors, which provide a voltage proportional to the received lighting flux.
The brightness modulating the electronic beam takes simultaneously into account these controls and corrections.
During test of the red gun, the brightness control is replaced by a fixed voltage.
To provide these capabilities, the brightness control circuit is organized as follows :
- light sensor voltage output
- brightness signal reception and selection
- brightness generation
- selection of normal and red gun test brightnesses.
(c) G1 amplifier
When failures are detected by the CRT protection circuit, it sends a binary signal to the CRT G1 grid inhibition circuit. The CRT is then cut off to preserve it from destruction.
This function is achieved by inserting a G1 amplifier circuit between the CRT protection circuit and the grid. This circuit effectively cuts off supply to the grid in the event a fault is detected.
When failures are detected by the CRT protection circuit, it sends a binary signal to the CRT G1 grid inhibition circuit. The CRT is then cut off to preserve it from destruction.
This function is achieved by inserting a G1 amplifier circuit between the CRT protection circuit and the grid. This circuit effectively cuts off supply to the grid in the event a fault is detected.
(d) Deflection and correction circuits
1 Correction circuits
The correction circuits provide compensation for two types of defaults:
The correction circuits provide compensation for two types of defaults:
- Pin cushion distorsion on the Y axes
- Linearity distorsion on both X and Y axes.
2 Deflection circuits
Considering the final purpose of this display unit, two types of scanning are used:
Deflection circuits are identical on X and Y channels.
A power saver circuit is used. This circuit saves the power which is dissipated in the deflection amplifier power stage, by modulating the voltage of the power supply, according to the speed of the drawing.
The switching time of this circuit is less than 500 ms.
Considering the final purpose of this display unit, two types of scanning are used:
- Greek-type scanning with defocusing for the background colored areas (Sky/Ground on the PFD, weather radar on the ND, grey rectangles used on the various DUs to enhance the legibility of information (e.g. those used on the PFD for the SPD, ALT, V/S, HDG scales)
- Stroke Scanning for symbology.
Deflection circuits are identical on X and Y channels.
A power saver circuit is used. This circuit saves the power which is dissipated in the deflection amplifier power stage, by modulating the voltage of the power supply, according to the speed of the drawing.
The switching time of this circuit is less than 500 ms.
(e) Misconvergence correction
Two types of adjustments are provided:
Two types of adjustments are provided:
- Static convergence
3 pairs of beam benders are used to adjust the beam position on screen center - Dynamic convergence
Convergence coils are used to adjust the beam on a screen corner.
(f) Monitoring circuits
These circuits monitor the deflection and color unblank inputs.
In the event of a failure, these inputs are replaced by an internal test pattern producing a dedicated white pattern on the screen (diagonal line).
In addition, these devices contain an orbiting circuit which makes the whole picture slightly move on the screen in a circular motion in order to avoid burning those phosphor elements which would be constantly striken for the display of fixed elements.
The period of picture movement is about 30 seconds.
These circuits monitor the deflection and color unblank inputs.
In the event of a failure, these inputs are replaced by an internal test pattern producing a dedicated white pattern on the screen (diagonal line).
In addition, these devices contain an orbiting circuit which makes the whole picture slightly move on the screen in a circular motion in order to avoid burning those phosphor elements which would be constantly striken for the display of fixed elements.
The period of picture movement is about 30 seconds.
(g) Protection circuits
The protection circuits are provided for phosphor protection and continuous self-test of the DU. They monitor the low voltage power supplies and the beam movements.
Minimum programmable authorized beam speed : 0.625 mm/microsecond.
In the event of a failure, the CRT is inhibited by G1 and the DU ANOMALY signal is positioned.
A temperature switch detects any abnormal temperature rise.
A thermo switch cuts off the power supply when internal temperature rises over a dangerous level.
Line fuses : they protect the line against power supply input short circuit, and against eventual lightning strike effects.
The protection circuits are provided for phosphor protection and continuous self-test of the DU. They monitor the low voltage power supplies and the beam movements.
Minimum programmable authorized beam speed : 0.625 mm/microsecond.
In the event of a failure, the CRT is inhibited by G1 and the DU ANOMALY signal is positioned.
A temperature switch detects any abnormal temperature rise.
A thermo switch cuts off the power supply when internal temperature rises over a dangerous level.
Line fuses : they protect the line against power supply input short circuit, and against eventual lightning strike effects.
(h) Red color gun monitoring
Basically the red color gun is controlled by internal DU circuitry, provided that the SG supplies the specific reserved color code.
The DU sends back to the DMC, the DU beam test results, via the DSDL feedback line.
Basically the red color gun is controlled by internal DU circuitry, provided that the SG supplies the specific reserved color code.
The DU sends back to the DMC, the DU beam test results, via the DSDL feedback line.
(4) Symbol generator
(a) General
The Symbol Generator is designed around 3 VLSI circuits.
Seven other LSI circuits have been specially designed to allow the implementation of the SG unit in the DU. The main functions of the SG are the following:
Inputs:
The Symbol Generator is designed around 3 VLSI circuits.
Seven other LSI circuits have been specially designed to allow the implementation of the SG unit in the DU. The main functions of the SG are the following:
- Drawing Program Control
- Drawing Execution
- Color, Blanking and Brightness Control
- Information exchange Control with the DMC.
- the SG program memory is partly RAM and partly EEPROM. PFD, ENGINE and parts of the ND programs are memorized in the EEPROM area. Other programs in process are teleloaded from the DMC at each mode change via the 800 Kbit/s serial link DSDL
- current data come from the DMC via the serial link and stored in the SG Memory by Direct Memory Access without any decrease in the drawing speed. Feedback data from the DU to the DMC are also obtained by Direct Memory Access
- Greek-type scanning for the background colored areas is done by the SG
- The alphanumeric characters are contained in EEPROM implemented in the SG program and data address field.
Inputs:
- 3 color bits coming from the WXR board in the DMC, via three digital serial lines (8 Mbits/s per line)
- 1 clock signal used to fetch the WXR color bits (8MHz).
- 2 analog outputs for the spot position (X and Y)
- 3 analog outputs for RGB video.
- Dedicated serial link with the DMC (800 Kbit/s) : DSDL.
(b) Description
The SG can be divided in several functional blocks :
The SG can be divided in several functional blocks :
1 Processor Chip and Computation Chips
Three VLSI circuits are the "heart" of the SG. These 3 chips constitute a very powerful programmable graphic processor. Its principal function is to control the spot position, the drawing speed and the blanking according to the commands of the drawing program. They give a new spot position every 500 ns (2 MHz).
Three VLSI circuits are the "heart" of the SG. These 3 chips constitute a very powerful programmable graphic processor. Its principal function is to control the spot position, the drawing speed and the blanking according to the commands of the drawing program. They give a new spot position every 500 ns (2 MHz).
2 Sine/cosine Memory
These 2x(4Kx12) PROMs convert the angle delivered by the Processor chip in two increments for the X and Y computation chips. For each angle value theta, this memory contains ; sin theta, cos theta, 0.075 sin theta.
This allows the number of drawing speeds available to be doubled artificially (16 instead of 8).
This device allows the speed to be adjusted in order to optimize power consumption.
These 2x(4Kx12) PROMs convert the angle delivered by the Processor chip in two increments for the X and Y computation chips. For each angle value theta, this memory contains ; sin theta, cos theta, 0.075 sin theta.
This allows the number of drawing speeds available to be doubled artificially (16 instead of 8).
This device allows the speed to be adjusted in order to optimize power consumption.
3 Interpolator
The two functions of this LSI circuit designed in HCMOS technology are:
The two functions of this LSI circuit designed in HCMOS technology are:
- to demultiplex the 2 x 6 bit outputs of the computation chips in 12 bits, in order to drive the Digital to Analog Conversion
- to compute, according to the two last values given by the computation chips, 3 intermediate positions of the spot in 500 ns period. This interpolation allows the exact position of the spot to be known every 125 ns and consequently to be able to change the color or the blanking signal with more precision in order to improve drawing quality.
4 Digital/Analog Converters
Two identical hybrid circuits (one for each way) are used for the digital to analog conversion, sampling and smoothing of the spot position signals.
Two identical hybrid circuits (one for each way) are used for the digital to analog conversion, sampling and smoothing of the spot position signals.
5 Masks
This circuit is able to furnish for each of the two masks a signal indicating if the spot is in or out of the mask. The accuracy of this indication is 125 ns thanks to the precise position given by the interpolator. The limits of the masks are contained in a RAM and consequently can be easily modified. The drawing of the mask limits is done by the SG itself.
This circuit is able to furnish for each of the two masks a signal indicating if the spot is in or out of the mask. The accuracy of this indication is 125 ns thanks to the precise position given by the interpolator. The limits of the masks are contained in a RAM and consequently can be easily modified. The drawing of the mask limits is done by the SG itself.
- The SG has 2 identical external masks in addition to the 2 internal windows of the processor and computation chips. The output signals of the external window circuits can be used as a blanking signal or to change the color.
6 Color control
The functions of this LSI circuit are :
4 color codes can be stored in 4 registers. This permits either to change normally the color by software or to switch in real time among the possibilities according to the color choice bits.
The available colors are presented on the following table.
The functions of this LSI circuit are :
- to change the color according to the program commands
- to switch the color according to the color choice bits which can be internal window or mask signals
- to multiplex the color bits coming from the SG and those coming from the WXR
- to program a delay on the color bits to provide adaptability between digital and analog circuits taking into account devices dispersion.
4 color codes can be stored in 4 registers. This permits either to change normally the color by software or to switch in real time among the possibilities according to the color choice bits.
The available colors are presented on the following table.
| ------------------------------------------------------------------------------- |
| ! CODES ! COLORS ! RED ! GREEN ! BLUE ! |
| ! ! ! (%) ! (%) ! (%) ! |
| !-----------------------------------------------------------------------------! |
| ! 00 ! Red gun control ! 100 ! 0 ! 0 ! |
| ! 01 ! White/Black ! 50 ! 100 ! 75 ! |
| ! 02 ! White/Cyan ! 50 ! 90 ! 60 ! |
| ! 03 ! Magenta/Black ! 80 ! 5 ! 80 ! |
| ! 04 ! White/Brown ! 30 ! 80 ! 85 ! |
| ! 05 ! Green/Brown ! 0 ! 90 ! 30 ! |
| ! 06 ! Cyan/Cyan ! 10 ! 70 ! 85 ! |
| ! 07 ! Yellow/Black ! 80 ! 100 ! 0 ! |
| ! 08 ! Cyan/Brown ! 0 ! 75 ! 85 ! |
| ! 09 ! Amber/Black ! 90 ! 50 ! 0 ! |
| ! 0A ! Yellow/Black 50% ! 40 ! 50 ! 0 ! |
| ! 0B ! Red 50% ! 50 ! 0 ! 0 ! |
| ! 0C ! Cyan ! 0 ! 65 ! 85 ! |
| ! 0D ! White 100% NU ! 100 ! 100 ! 100 ! |
| ! 0E ! Pattern ! 1 ! 1 ! 1 ! |
| ! 0F ! Grey background ! 18 ! 33 ! 24 ! |
| ! 10 ! Red gun cont prep. ! 0 ! 0 ! 0 ! |
| ! 11 ! White 75% ! 35 ! 75 ! 55 ! |
| ! 12 ! Brown ! 20 ! 15 ! 0 ! |
| ! 13 ! White 50% ! 20 ! 50 ! 35 ! |
| ! 14 ! Green/Cyan ! 0 ! 100 ! 0 ! |
| ! 15 ! NU Red 100% ! 100 ! 0 ! 0 ! |
| ! 16 ! NU Blue 100% ! 0 ! 0 ! 100 ! |
| ! 17 ! NU Green 76% ! 0 ! 76 ! 0 ! |
| ! 18 ! NU ! 0 ! 0 ! 0 ! |
| ! 19 ! WXR synchro ! 0 ! 0 ! 0 ! |
| ! 1A ! Blue ! 0 ! 65 ! 85 ! |
| ! 1B ! Magenta ! 65 ! 0 ! 85 ! |
| ! 1C ! Red ! 75 ! 0 ! 0 ! |
| ! 1D ! Yellow WXR ! 100 ! 70 ! 0 ! |
| ! 1E ! Green ! 10 ! 65 ! 0 ! |
| ! 1F ! Blank ! 0 ! 0 ! 0 ! |
NOTE: NU codes for test purposes only.
NOTE: The Weather Radar can use only the last 8 codes of the list.
7 Memory block
Memory of the SG is divided in 4 parts:
Memory of the SG is divided in 4 parts:
a 6K 16 bit-words in EEPROM for the monitor program and the alphanumerics,
b 10K 16 bit-words in EEPROM for the PFD, ENGINE, and part of the ND programs.
c 15K 16 bit-words in RAM for current drawing program and data divided in:
- 2 pages of 1K words each for rapidly refreshed data
- 2 pages of 5K words each for slowly refreshed data
- 1 non paginated 3K for feedback data.
d 1K 16 bit-word, located on a 1K word address field, for DUA (DU anomaly).
At any time, one page is used by the SG to build the current image while the other page receives via the serial link the necessary data for the next image.
The EEPROMs will be programmed via the DSDL line. This shall take place only at the electrical power on setting (DMC + DU), and only if the program stored in the EEPROM does not match that which corresponds to the DMC software. There is no specific circuit on the SG to program the EEPROM "in situ".
The RAMs are protected against short power interrupt (at least 3 seconds).
At any time, one page is used by the SG to build the current image while the other page receives via the serial link the necessary data for the next image.
The EEPROMs will be programmed via the DSDL line. This shall take place only at the electrical power on setting (DMC + DU), and only if the program stored in the EEPROM does not match that which corresponds to the DMC software. There is no specific circuit on the SG to program the EEPROM "in situ".
The RAMs are protected against short power interrupt (at least 3 seconds).
NOTE: The alphanumerics field contains the description of standard alphanumerics (available in 4 sizes) on one hand, and of special drawing characters on the other hand. The sizes are : 3, 3.5, 4 and 5 mm.
8 Inputs/outputs controller
The I/O controller provides the timing for the SG system. It controls all the memory accesses and allows a shared memory access between the processor and the serial link interface.
The I/O controller provides the timing for the SG system. It controls all the memory accesses and allows a shared memory access between the processor and the serial link interface.
9 Serial link controller : SDL
This function includes:
This function includes:
- a Transmitter/Receiver circuit which performs the Serial/Parallel conversion, based on the Harris device HS 3282
- a LSI circuit whose function is to interface the serial link with the memory. It handles the direct memory access and generates the control signals according to the labels sent by the DMC
- a line driver circuit whose function is to interface the HS 3282 and the DSDL feedback line.
10 Clock generator
The LSI circuit generates all the necessary clocks for the SG. The clock reference is a 16MHz oscillator, which must be matched with the WXR clock of the DMC.
The LSI circuit generates all the necessary clocks for the SG. The clock reference is a 16MHz oscillator, which must be matched with the WXR clock of the DMC.
a WXR link decoder
The functions of this circuit are:
The functions of this circuit are:
- To receive the color bits and clock signals
- To extract the frame synchro signal
- To reset the FIFO memory and to enable the writing
- To trigger the LSI symbol generator.
b FIFO memory
The size of the FIFO memory (64 x 3) is sufficient to take care of the slight frequency difference between the SG oscillator and the DMC WXR oscillator.
The size of the FIFO memory (64 x 3) is sufficient to take care of the slight frequency difference between the SG oscillator and the DMC WXR oscillator.
12 Safety function
a SG self test
The SG is able to be self tested because its digital outputs X, Y, blanking and color are connected via a test register on the SG bus.
The SG is able to be self tested because its digital outputs X, Y, blanking and color are connected via a test register on the SG bus.
b Watch dog
A watching circuit controls the activity of SG LSI, and of the DSDL link.
It is retriggered by the INIT signal which is supplied by the SG after reception of status word by the DSDL.
When the watch dog falls, then the DSDL receiver is re-initialized one time.
A watching circuit controls the activity of SG LSI, and of the DSDL link.
It is retriggered by the INIT signal which is supplied by the SG after reception of status word by the DSDL.
When the watch dog falls, then the DSDL receiver is re-initialized one time.
c Short power interrupt detection : SPID
Power interrupts shorter than 2 ms will not induce any change of the DU state.
Power interrupts less than 3 seconds will not destroy the program RAMs content, but MASK RAMs will need reloading.
In this case, a short power interrupt signal will be generated.
More than 3 seconds power interrupts can destroy all RAMs content.
A long power interrupt signal will then be provided.
Power interrupts shorter than 2 ms will not induce any change of the DU state.
Power interrupts less than 3 seconds will not destroy the program RAMs content, but MASK RAMs will need reloading.
In this case, a short power interrupt signal will be generated.
More than 3 seconds power interrupts can destroy all RAMs content.
A long power interrupt signal will then be provided.
d DU temperature
Two temperature levels are detected:
Two temperature levels are detected:
- The lowest one generates an alarm
- The second one cuts off the DU.
e DU anomaly
This signal results from a failure considered as possibly dangerous for the CRT.
The failures are:
This signal results from a failure considered as possibly dangerous for the CRT.
The failures are:
- plus or minus 5V, plus or minus 15V, + 100V, - 170V trouble detection
- Cathode amplifiers over-load detection
- Beam minimum velocity monitoring
- VHV anomaly.
(5) Interconnection board
The interconnection board is located at the rear of the display unit and electrically interconnects the lateral boards by flexible circuit and connectors. The interconnection board includes the DU connector and several components, including lightning protection, line fuses, Normal/Alternate and DU ON/OFF relays.
The interconnection board is located at the rear of the display unit and electrically interconnects the lateral boards by flexible circuit and connectors. The interconnection board includes the DU connector and several components, including lightning protection, line fuses, Normal/Alternate and DU ON/OFF relays.
NOTE: These relays are driven by discrete signals. The DU OFF discrete is generated by the brightness knob.
(6) Low voltage power supply
Low voltage power supply consists of two parts:
This structure permits the use of small size transformers, the second part operating from a constant input voltage and thus minimizing the filtering components.
Low voltage power supply consists of two parts:
- the first one provides an intermediate pre-regulated 40 V voltage
- the second one provides, via two parallel transformers, all the necessary voltages to the different modules of the DU:
| -6.3 V CRT |
| 25 V VHV |
| 5 V Symbol generator |
| -170 V ! |
| 100 V ! |
| +34 V ! |
| -34 V ! |
| +17 V ! Analog board |
| -17 V ! |
| +15 V ! |
| -15 V ! |
This structure permits the use of small size transformers, the second part operating from a constant input voltage and thus minimizing the filtering components.
(7) DU reactions to power interrupts
| ------------------------------------------------------------------------------- |
| ! POWER INTERRUPT ! CONSEQUENCE ! |
| !------------------------!----------------------------------------------------! |
| ! t < 2.5 ms ! No effect ! |
| !------------------------!----------------------------------------------------! |
| ! ! . LV power supply restarts within 200 ms. ! |
| ! 2.5 ms < t < 3 s ! . VHV power supply restarts within 300 ms after ! |
| ! ! recovery of LV power (= 500 ms global). ! |
| ! ! . Masks RAMs may be lost. ! |
| !------------------------!----------------------------------------------------! |
| ! 3 s < t < 11 s ! . Same as above, plus : ! |
| ! ! . All RAM contents may be lost. ! |
| !------------------------!----------------------------------------------------! |
| ! t > 11 s ! . Same as above, plus : ! |
| ! ! . Cathode heating temporization (about 12 seconds).! |
NOTE: In any case, the DU is able to dialogue with the DMC as soon as the LV power supplies are available, i.e. 200 ms after the main power is on.