FLIGHT CONTROL DATA CONCENTRATOR (FCDC) - DESCRIPTION AND OPERATION

** ON A/C NOT FOR ALL

1. General
The Flight Control Data Concentrator (FCDC) is a part of the Electrical Flight Control System (EFCS).
It is a centralized subsystem that provides access to EFCS status and failure information.
The function of the FCDC is based on the validation and concentration of in-flight and on-ground status and failure data.
The result of this operation will be stored in the FCDC failure memory or sent back to the EFCS or transmitted to associated A/C subsystems.

** ON A/C NOT FOR ALL

2. Component Location

FCDC - Location

FIN	FUNCTIONAL DESIGNATION	PANEL	ZONE	ATA REF
** ON A/C ALL
3CE1	FCDC-1	83VU	127	27-95-34
3CE2	FCDC-2	84VU	128	27-95-34
3CE1	FCDC-1		127	27-95-34
3CE2	FCDC-2		128	27-95-34
3CE1	FCDC-1	83VU	127	27-95-34
3CE2	FCDC-2	84VU	128	27-95-34

** ON A/C NOT FOR ALL

3. Power Supply
The FCDC 1 is supplied from DC essential bus bar 8PP and the FCDC 2 is supplied from DC normal bus bar 2PP.
(Ref. 27-90 ELEC PWR SPLY - GENERAL)

FCDC Functional Blocks

A. Electrical Power

Block Diagram of Power Supply for FCDC

(1) Power supply
The power supply is a two-stage power converter consisting of the following functional blocks :

the input EMI-filter
the boost stage
the DC/DC converter stage
the voltage monitor

The module contains in addition to the basic functions, input protection circuits to cope with lightning strikes (category 1) and control circuits for overvoltage (30.3V) and undervoltage (18.5V) conditions.
The output section of the power supply contains separate secondary windings for the plus or minus 15V supply. For safety reasons, there are five linear regulators each supplying an I/O section with plus or minus 15V.

I/O Supply Arrangement

If one regulator fails, the performance of the others is not affected.
The output voltage is monitored.
Failure signals are generated in the case of over or undervoltage.
The power supply has sufficient stored energy to allow the equipment full performance for power interrupts of up to 10ms. In the case of power interrupts longer than 10ms, a system reset signal is generated by the power supply module. The equipment continues operation when the input voltage is again within limits.

(2) Power supply monitoring
The monitor consists of the following four indepedent monitor blocks :

Block Diagram of Power Supply for FCDC

the boost input voltage monitor
the boost overvoltage monitor
the DC/DC converter input voltage monitor
the DC/DC converter output voltage monitor

For internal use, an auxiliary voltage is generated by a linear regulator.

(3) Power Dissipation
The FCDCs have a typical power dissipation of 20 Watts.

** ON A/C NOT FOR ALL

4. Interface

FCDC General Interface

** ON A/C NOT FOR ALL

5. Component Description

FCDC Functional Blocks

[3CE1] [3CE2]
The FCDC is an assembly of seven basic modules:

housing
ARINC 600 connector
protection board
mother board
CPU/PS board
I/O board
OBRM

A. General

(1) Electronic design
The FCDC is housed in a 2MCU casing in accordance with the ARINC standard 600.
The connections to the A/C wiring are via an ARINC 600 size 2 connector.
The FCDC contains five types of Shop Replaceable Units (SRU). These are :

CPU/PS board
I/O board
OBRM
protection board
mother board

The configuration of these modules within the FCDC box is shown in

Configuration of Modules within the FCDC

The power dissipation of the FCDC is 10W.

(2) Mechanical design
The mechanical design of the FCDC has led to the following results :

(a) ARINC 600 case, size 2MCU, size 2 connector.

(b) The FCDC box contains two printed circuits boards :

1 one board divided into two modules : the processor module and the power supply module.

2 one board dedicated to the five I/O modules :

I/O modules 1 and 3 : ELAC 1/SEC 1
I/O modules 2 and 4 : ELAC 2/SEC 2/SEC 3
I/O module 5 : CFDIU/FWCs.
These boards are inserted from the front of computer.
The connection between the I/O board and CPU board is ensured by three flat cables (16 bits I/O data bus).

(d) The back panel assy contains the mother board, the I/O connector, the protection board and the power input connector :

1 The mother board and the I/O connector allow the interconnection between the ARINC connector and the functional board (I/O board) as regards the I/O signals.

2 the protection board and the power input connector allow the interconnection between the ARINC connector and the PS board as regards the power supply.

(e) The weight of the FCDC is 2.3 kg.

(f) The thermal design allows the equipment to operate for two hours without any air cooling.

B. Processor Board
The Block diagram shows the CPU/PS Board.

Block Diagram - Processor Board

(1) CPU
The 16-bit microprocessor MC 68000 is used as the CPU for the FCDC.

(2) Clock generator
APP clocks of the FCDC are derived from a single crystal oscillator (10 MHz).

(3) Timer
A timer with a time base of 2.0 ms is implemented to provide a real-time base for the software cycles.
A second timer is provided to supervise the handshaking on the bus. If a time out occurs, the bus cycle is aborted and the processor enters a trap routine to handle this exceptional condition.
A third type of timer is a watchdog timer. The CFU must reset this counter every 25 ms by accessing a specific address.

(4) Interrupt system
A real-time clock (RTC) with an interval time of 2.0 ms is also derived from the CPU clock. This real time clock interrupts the CPU on level 3.
An interrupt occurs on level 1 when the watchdog timer sends a timeout signal. This timeout signal indicates that the watchdog timer has not been reset for 25 ms by the system software.
An interrupt on level 7 can be generated for test purposes.
Interrupt summary :

--------------------------------------------------------------

! level ! event - source !

!-----------!------------------------------------------------!

! 1 ! time-out - watchdog !

! 2 ! not used !

! 3 ! 2.0 ms - RTC !

! 4-7 ! not used !

! exception ! exceptions - H/W- or prog. failure !

! reset ! reset - power-on, BITE !

--------------------------------------------------------------

Remarks : 1 ->lowest,

2 ->highest interrupt level

(5) Memories
Four different types of memories are implemented on the CPU/PS board :

System Internal EPROM (16 Kbytes)
EEPROM (32 Kbytes)
RAM (16 Kbytes)
OBRM EPROM (256 Kbytes) (with 150 nsec access time) initialization, BITE.

(6) Power loss monitoring
Facilities are provided to monitor the duration of a power interrupt.
If a power-shutdown occurs and the power returns within 3 seconds, a discrete signal will be set to "0". If not, the signal will be "1".
Five additional discrete signals indicate the status of the secondary plus or minus 15V power lines for the I/O sections.
A "0" indicates that the corresponding I/0 section is supplied with plus or minus 15V.
A discrete signal is also used to monitor the "FCDC FAIL" relay position.

C. Program Memory Module

(1) Characteristics
A plug-in memory module is implemented in the doghouse of the box. This EPROM-type memory has a capacity of 256 Kbytes shared in 224 Kbytes for application software and 32 Kbytes (protected) for ground test software.
It is directely connected to the processor module by a 53-pins connector.

(2) Operation
To change the program, it is necessary to simply remove the module from the doghouse and insert a reprogammed version.
Removal of the program memory module causes the processor to go into a defined halt state.
The insertion of the program memory module initiates the restart and self-test procedure.
The on-ground test software is used for shop maintenance, the access to this software is protected (to avoid an untimely access during operational mode) by means of a mechanism which leads, in case of activation, to a FCDC FAULT on A/C.

Software Selection - Flow Chart

D. I/O Interfaces
The I/O interfaces provide the required input/output protection, conditioning and buffering for ARINC 429, discrete and analog signals.
The maximum number of I/O signals can be :

15 ARINC 429 input channels (low speed)
5 ARINC 429 input channels (low speed for internal wraparound)
5 ARINC 429 output channels (low speed)
40 discrete inputs
20 discrete outputs
4 analog inputs.

These signals are subdivided into five independent sections. Four of these sections are completely identical and are realized by pairs on two boards.
The remaining fifth section is allocated to a third I/O board.
There is no direct data flow between two I/O sections. The communication is completely under the control of the processor module.

(1) I/O sections 1 to 4
The I/O sections 1 to 4 are dedicated to the EFCS computers (ELAC and SEC).

Block Diagram of I/O (INPUT/OUTPUT) - Section 1 to 4

The block diagram shows the major components of one I/O section. These are :

bus interface
access support
ARINC 429 input/output
discrete inputs
discrete outputs.

(a) Bus interface
The interface to the processor module consists of a 16-bit bi-directional driver for data, as well as buffered address and control lines.

(b) Access support circuit
The access support circuit decodes address signals, generates control signals and buffers intermediate data.

(c) ARINC 429 inputs/outputs
The ARINC 429 section is designed to receive and transmit signals according to the ARINC specification.
The design is based on HARRIS HS-3282 and HS-3182 chips.
The configuration is illustrated.

ARINC 429 Interface (I/O 1-3 or I/O 2/4)

Each HS-3282 chip contains signal conditioning, buffering and monitoring for two input channels.
An additional driver (HS 3182) is needed for an output channel.

(d) discrete inputs
The discrete input circuit is designed for an optional signal of both "GND/OPEN" or "OPEN/28V" polarities.

Block Diagram of Discrete Inputs

The block diagram shows the basic configuration :

the discrete input signals of sections 1 and 3 are implemented on one hybrid component (4 discrete inputs)
the discrete input signals of sections 2 and 4 are implemented on one hybrid component (4 discrete inputs)
for every input channel, the hybrid component contains passive low pass filter, a bus driver and a test signal driver.

the discrete inputs are filtered by a low pass RC filter with a typical time constant of 15 ms.

(e) discrete outputs
The discrete output interface is designed for "GND/OPEN" signals.
Electromechanical non-latching relays are used to achieve optimum isolation between the FCDC and the outside electronics

Basic Discrete Output Circuit

One set of relay contacts is reserved for test purpose.

(2) I/O section 5
The I/O section 5 is designed to meet the requirements of various A/C subsystems.
In addition to the types of interfaces implemented in section 1 to 4, analog input signals have to be received and converted by this section.

Block Diagram of I/O - Section 5

The block diagram shows the organization and data flow in this section.
These components are :

ARINC 429 inputs
ARINC 429 outputs
discrete inputs
discrete outputs
analog inputs.

(a) ARINC 429 inputs/outputs
The implementation of the ARINC 429 input/output channels is identical to the configuration of section 1 to 4.

(b) Analog input interface
The block diagram shows the interface with major components:

Block Diagram of Analog Input Interface

Multiplexer
Differential Amplifier
Analog/Digital converter.

The time period for a complete conversion cycle of an input signal is approx 35 microsec.

(c) Discrete inputs/outputs
There are only minor differences concerning the discrete input/output interfaces as compared with section 1 to 4.
20 discrete inputs are implemented on 3 hybrid components (2 components of 8 inputs and 1 component of 4 inputs).
The discrete input signals are protected by an extra filter module.

E. Input/Output Protections
The FCDC contains filtering components for the input/output and supply lines which protect the unit against unlimited destruction or permanent degradation in case of :

spurious application of 28VDC or 115VAC signals on ARINC connector pins
effect of lightning strikes
imported electrical noise.

The filters also protect against the exportation of electrical interference from the FCDC to other electronic equipment within the A/C.
To achieve this objective, each input/output line is provided with the appropriate components. Particular attention is given to the internal wiring segregation : wiring between the ARINC connector and the different I/O sections.

** ON A/C NOT FOR ALL

6. Operation
FCDC functions :

A. Data Concentration
Based on data received from ELACS, SECS and various other sources, the FCDC generates and transmits the following digital information to the ECAM system :

the position and availability of flight control surfaces
failure signals.

The FCDC commands also the illumination of the lights indicating the priority between side sticks. But the side sticks priority logic is implemented inside the ELAC and SEC.

B. Maintenance Functions
The above information is also transmitted to the Centralized Fault Display Unit.

C. Particular Points

In the event of multiples failures affecting certain LRUs of a same type, the FCDC will, in certain cases, give only one message;
(e.g left and right throttles failed: one message only
However, if accelerometers 1 and 2 failed: two messages).
The surface position is given by the computer which controls the surface except for the ailerons, the position is given by the computer in standby
The indication SPOILER OUT is given for a deflection higher than 2.5 deg.
Some periodic tests are performed by the FCDC
Test generated by the FCDC: Damping test

** ON A/C NOT FOR ALL

7. Test

A. General
The FCDC is equipped with integrated test functions which provide a high degree of failure detection, identification and isolation. Confirmed failures are stored in a particular zone of non-volatile memory for later display in a maintenance mode.

B. Self Test

(1) Basic Test
Upon power-on, the FCDC is initialized and starts its internal self test-functions (BITE). These are :

FCDC-BITE Access

partial BITE if power supply interrupt is less than 3 seconds A/C on ground or if power supply interrupt is more than 3 seconds A/C in flight
complete BITE if power supply interrupt is more than 3 seconds A/C on ground.

(2) Memory
A bytewise checksum method is employed to check the correct operation of each half of the EPROM-type memories.
To check if all local RAM memory cells can be set and cleared, two bit patterns, Hex "5555" and Hex "AAAA", are written to each RAM memory location and read back.

(3) Timers
The real time counter is tested initially for correct operation by measuring the elapsed time between two successive interrupts.
The two other timers (bus time out supervisor and watchdog timer) are then checked to ensure that they expire and generate a failure signal if they are not reset in time.

(4) ARINC 429 Channels
The two inputs and the output of each ARINC 429 chip are tested using wraparound techniques.
On a first level (digital signals), both receivers are provided with the actual information from the transmitter of the chip. The test result is achieved from the comparison of the transmitted word with the received word.
On a second level (analog signals), a comparison test is performed using the permanent wraparound connection from the driver output to an extra input channel.
After having checked the correct operation of each channel, faulty messages are simulated to test the failure recognition capability of the receiver channels.

(5) Discrete Inputs/Outputs
The discrete input interfaces are tested using a dedicated test line which is first connected to VCC and then to GND. If the outputs correspond to the polarity of the test line, the interface has passed the test.
The discrete outputs (relays) have two contacts. One of these contacts is used for test purposes as follows:
The position of the relay contacts (open, closed) is read and then compared with the actual test pattern.

(6) Analog Inputs
One channel of the analog input interface is permanently connected to a fixed voltage derived from the A/D converter. The corresponding digital output value is read and compared with a permitted tolerance band.

(7) Power Supply
The discrete signals of the monitored secondary output voltages of plus or minus 15V are read and checked for validity.

C. System Test
The correct operation of the EFCS is checked through the exchange of information among the ELAC, SEC and FCDC computers.
These system tests are initialized either automatically or manually.

D. In-Flight Monitoring
Self testing is performed periodically (scheduled in normal mode).

E. Maintenance Mode
The menu mode is initiated via commands from the CFDIU.
A menu-driven control technique is applied for communication between the FCDC and the CFDIU. The FCDC transmits on demand the contents of the non-volatile memory either in plain English or in hexadecimal format.
In addition to the display of failure information, all types and levels of tests can be initiated using predefined commands.

F. Digital Output Interface

-----------------------------------------------------------

FCDC 1 TO

-----------------------------------------------------------

Bus N°1 (DGO 1/5) FWC1,CFDIU,FMGC1,DMC1,DMC3,DMU

Bus N°2 (DGO 2/5) FWC2,FMGC2,DMC2,DMU

Bus N°3 (DGO 1/1) ELAC1 COM,FCDC OPP

Bus N°4 (DGO 1/3) SEC1 MON

Bus N°5 (DGO 1/2) SEC2 COM,SEC3 COM

Bus N°6 (DGO 1/4) ELAC2 MON

-----------------------------------------------------------

FCDC 2 TO

-----------------------------------------------------------

Bus N°1 (DGO 1/5) FWC2,FMGC2,DMC2,FDIU

Bus N°2 (DGO 2/5) FWC1,CFDIU,FMGC1,DMC1,DMC3

Bus N°3 (DGO 1/1) SEC1 COM,FCDC OPP

Bus N°4 (DGO 1/3) ELAC1 MON

Bus N°5 (DGO 1/2) ELAC2 COM

Bus N°6 (DGO 1/4) SEC2 MON,SEC3 MON

-----------------------------------------------------------

G. Digital Outputs: FCDC's Bus 1&2.

-------------------------------------------------------------------------------

| PARAMETER LIST PARAMETER CHARACTERISTICS (NUMERIC) |

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

1 040 01 !EFCS-DIS ! ! ! ! ! ! ! ! !

2 040 10 !STATUS ! ! ! ! ! ! ! ! !

!WORD 1 ! ! ! ! !240 !DIS ! ! !

! ! ! ! ! ! ! ! ! !

!SDI ! ! ! ! 9 ! ! ! ! !

!SDI ! ! ! ! 10 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!PITCH LAW ! ! ! ! ! ! ! ! !

!CODE 1 !bit Status 1! ! ! 11 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!PITCH LAW ! ! ! ! ! ! ! ! !

!CODE 2 !bit Status 1! ! ! 12 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!PITCH LAW ! ! ! ! ! ! ! ! !

!CODE 3 !bit Status 1! ! ! 13 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!Spare ! ! ! ! 14 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!PITCH ! ! ! ! ! ! ! ! !

!DIRECT ! ! ! ! ! ! ! ! !

!CONTROL !bit Status 1! ! ! 15 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ROLL LAW ! ! ! ! ! ! ! ! !

!CODE 1 !bit Status 1! ! ! 16 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ROLL LAW ! ! ! ! ! ! ! ! !

!CODE 2 !bit Status 1! ! ! 17 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 1 or ! ! ! ! ! ! ! ! !

!ELAC 2 ! 1 = ELAC 1 ! ! ! ! ! ! ! !

!ACTIVE ! 0 = ELAC 2 ! ! ! 18 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 1 ! ! ! ! ! ! ! ! !

!PITCH ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 19 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 1 ! ! ! ! ! ! ! ! !

!ROLL FAULT!bit Status 1! ! ! 20 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 2 ! ! ! ! ! ! ! ! !

!PITCH ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 21 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 2 ! ! ! ! ! ! ! ! !

!ROLL FAULT!bit Status 1! ! ! 22 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 1 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 23 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 2 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 24 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 1 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 25 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 2 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 26 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!THS CMD ! ! ! ! ! ! ! ! !

!JAM !bit Status 1! ! ! 27 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!OPPOSITE ! ! ! ! ! ! ! ! !

!FCDC FAULT!bit Status 1! ! ! 28 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 3 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 29 ! ! ! ! !

-------------------------------------------------------------------------------

| PARAMETER LIST PARAMETER CHARACTERISTICS (NUMERIC) |

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

1 041 01 !EFCS-DIS ! ! ! ! ! ! ! ! !

2 041 10 !STATUS ! ! ! ! ! ! ! ! !

!WORD 2 ! ! ! ! ! 240! DIS! ! !

! ! ! ! ! ! ! ! ! !

!SDI ! ! ! ! 9 ! ! ! ! !

!SDI ! ! ! ! 10 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L AIL B ! ! ! ! ! ! ! ! !

!FAULT (1) !bit Status 1! ! ! 11 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L AIL G ! ! ! ! ! ! ! ! !

!FAULT (2) !bit Status 1! ! ! 12 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R AIL G ! ! ! ! ! ! ! ! !

!FAULT (1) !bit Status 1! ! ! 13 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R AIL B ! ! ! ! ! ! ! ! !

!FAULT (2) !bit Status 1! ! ! 14 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L ELEV B ! ! ! ! ! ! ! ! !

!FAULT (1) !bit Status 1! ! ! 15 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L ELEV G ! ! ! ! ! ! ! ! !

!FAULT (2) !bit Status 1! ! ! 16 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R ELEV B ! ! ! ! ! ! ! ! !

!FAULT (1) !bit Stauts 1! ! ! 17 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R ELEV Y ! ! ! ! ! ! ! ! !

!FAULT (2) !bit Status 1! ! ! 18 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!F/O ! ! ! ! ! ! ! ! !

!PRIORITY ! ! ! ! ! ! ! ! !

!LOCKED !bit Status 1! ! ! 19 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!CAPT ! ! ! ! ! ! ! ! !

!PRIORITY ! ! ! ! ! ! ! ! !

!LOCKED !bit Status 1! ! ! 20 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!LAF ! ! ! ! ! ! ! ! !

!ACTIVE !bit Status 1! ! ! 21 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!G AND Y ! ! ! ! ! ! ! ! !

!ACCU FAULT!bit Status 1! ! ! 22 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!LAF ! ! ! ! ! ! ! ! !

!DEGRADED ! ! ! ! ! ! ! ! !

!& AIL ! ! ! ! ! ! ! ! !

!PREDEFLECT!bit Status 1! ! ! 23 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!LAF ! ! ! ! ! ! ! ! !

!DEGRADED ! ! ! ! ! ! ! ! !

!SPLR ONLY !bit Status 1! ! ! 24 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!CHECK ! ! ! ! ! ! ! ! !

!IRS !bit Status 1! ! ! 25 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!LAF INOP !bit Status 1! ! ! 26 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!STABILIZER! ! ! ! ! ! ! ! !

!JAM !bit Status 1! ! ! 27 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!CAPT SSTU ! ! ! ! ! ! ! ! !

!INOP !bit Status 1! ! ! 28 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!F/O SSTU ! ! ! ! ! ! ! ! !

!INOP !bit Status 1! ! ! 29 ! ! ! ! !

-------------------------------------------------------------------------------

| PARAMETER LIST PARAMETER CHARACTERISTICS (NUMERIC) |

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

1 042 01 !EFCS-DIS ! ! ! ! ! ! ! ! !

2 042 10 !STATUS ! ! ! ! ! ! ! ! !

!WORD 3 ! ! ! ! ! 240! DIS! ! !

! ! ! ! ! ! ! ! ! !

!SDI ! ! ! ! 9 ! ! ! ! !

!SDI ! ! ! ! 10 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L AIL B ! ! ! ! ! ! ! ! !

!AVAIL (1) !bit Status 1! ! ! 11 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L AIL G ! ! ! ! ! ! ! ! !

!AVAIL (2) !bit Status 1! ! ! 12 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R AIL G ! ! ! ! ! ! ! ! !

!AVAIL (1) !bit Status 1! ! ! 13 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R AIL B ! ! ! ! ! ! ! ! !

!AVAIL (2) !bit Status 1! ! ! 14 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L ELEV B ! ! ! ! ! ! ! ! !

!AVAIL (1) !bit Status 1! ! ! 15 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L ELEV G ! ! ! ! ! ! ! ! !

!AVAIL (2) !bit Status 1! ! ! 16 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R ELEV B ! ! ! ! ! ! ! ! !

!AVAIL (1) !bit Status 1! ! ! 17 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R ELEV Y ! ! ! ! ! ! ! ! !

!AVAIL (2) !bit Status 1! ! ! 18 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 1 P/B! ! ! ! ! ! ! ! !

!SW OFF !bit Status 1! ! ! 19 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!ELAC 2 P/B! ! ! ! ! ! ! ! !

!SW OFF !bit Status 1! ! ! 20 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 1 ! ! ! ! ! ! ! ! !

!AVAIL !bit Status 1! ! ! 21 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 2 ! ! ! ! ! ! ! ! !

!AVAIL !bit Status 1! ! ! 22 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 3 ! ! ! ! ! ! ! ! !

!AVAIL !bit Status 1! ! ! 23 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 4 ! ! ! ! ! ! ! ! !

!AVAIL !bit Status 1! ! ! 24 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 5 ! ! ! ! ! ! ! ! !

!AVAIL !bit Status 1! ! ! 25 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!CHECK ADC !bit Status 1! ! ! 26 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 1 P/B ! ! ! ! ! ! ! ! !

!SW OFF !bit Status 1! ! ! 27 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 2 P/B ! ! ! ! ! ! ! ! !

!SW OFF !bit Status 1! ! ! 28 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 3 P/B ! ! ! ! ! ! ! ! !

!SW OFF !bit Status 1! ! ! 29 ! ! ! ! !

-------------------------------------------------------------------------------

| PARAMETER LIST PARAMETER CHARACTERISTICS (NUMERIC) |

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

1 043 01 !EFCS-DIS ! ! ! ! ! ! ! ! !

2 043 10 !STATUS ! ! ! ! ! ! ! ! !

!WORD 4 ! ! ! ! ! 240! DIS! ! !

! ! ! ! ! ! ! ! ! !

!SDI ! ! ! ! 9 ! ! ! ! !

!SDI ! ! ! ! 10 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L SPLR 1 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 11 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R SPLR 1 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 12 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L SPLR 2 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 13 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R SPLR 2 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 14 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L SPLR 3 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 15 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R SPLR 3 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 16 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L SPLR 4 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 17 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R SPLR 4 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 18 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L SPLR 5 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 19 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R SPLR 5 !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 20 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 1 POS! ! ! ! ! ! ! ! !

!VALID !bit Status 1! ! ! 21 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 2 POS! ! ! ! ! ! ! ! !

!VALID !bit Status 1! ! ! 22 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 3 POS! ! ! ! ! ! ! ! !

!VALID !bit Status 1! ! ! 23 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 4 POS! ! ! ! ! ! ! ! !

!VALID !bit Status 1! ! ! 24 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 5 POS! ! ! ! ! ! ! ! !

!VALID !bit Status 1! ! ! 25 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!GND SPLR !1 = OUT ! ! ! ! ! ! ! !

!OUT !0 = Retract ! ! ! 26 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!GND SPLR ! ! ! ! ! ! ! ! !

!ARMED !bit Status 1! ! ! 27 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPD BRK ! ! ! ! ! ! ! ! !

!COMMAND !bit Status 1! ! ! 28 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!AIL DROOP !bit Status 1! ! ! 29 ! ! ! ! !

-------------------------------------------------------------------------------

| PARAMETER LIST PARAMETER CHARACTERISTICS (NUMERIC) |

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

1 044 01 !EFCS-DIS ! ! ! ! ! ! ! ! !

2 044 10 !STATUS ! ! ! ! ! ! ! ! !

!WORD 5 ! ! ! ! ! 240! DIS! ! !

! ! ! ! ! ! ! ! ! !

!SDI ! ! ! ! 9 ! ! ! ! !

!SDI ! ! ! ! 10 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 1 ! ! ! ! ! ! ! ! !

!SPD BRK ! ! ! ! ! ! ! ! !

!LEVER ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 11 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 2 ! ! ! ! ! ! ! ! !

!SPD BRK ! ! ! ! ! ! ! ! !

!LEVER ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 12 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 3 ! ! ! ! ! ! ! ! !

!SPD BRK ! ! ! ! ! ! ! ! !

!LEVER ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 13 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 1 ! ! ! ! ! ! ! ! !

!GND SPLR ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 14 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 2 ! ! ! ! ! ! ! ! !

!GND SPLR ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 15 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SEC 3 ! ! ! ! ! ! ! ! !

!GND SPLR ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 16 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!L SSTU ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 17 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!R SSTU ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 18 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!Spare ! ! ! ! 19 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!Spare ! ! ! ! 20 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 1 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 21 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 2 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 22 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 3 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 23 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 4 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 24 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPLR 5 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 25 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPD BRK ! ! ! ! ! ! ! ! !

!LEVER ! ! ! ! ! ! ! ! !

!DISAGREE !bit Status 1! ! ! 26 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!SPD BRK ! ! ! ! ! ! ! ! !

!NOT USED !bit Status 1! ! ! 27 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!Spare ! ! ! ! 28 ! ! ! ! !

! ! ! ! ! ! ! ! ! !

!FLT CTL ! ! ! ! ! ! ! ! !

!CLASS 2 ! ! ! ! ! ! ! ! !

!FAULT !bit Status 1! ! ! 29 ! ! ! ! !

-------------------------------------------------------------------------------

| PARAMETER LIST PARAMETER CHARACTERISTICS (NUMERIC) |

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

1 301 01 !CAPT ROLL !+4/-20 !DEG ! 29 ! 11 ! 120!BNR ! ! !

2 301 10 !CMD POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 302 01 !F/O ROLL !+4/-20 !DEG ! 29 ! 11 ! 120!BNR ! ! !

2 302 10 !CMD POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 304 01 !RUDDER !+/-30 !DEG ! 29 ! 11 ! 120!BNR ! ! !

2 304 10 !PEDAL POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 305 01 !CAPT PITCH!+/-16 !DEG ! 29 ! 11 ! 120!BNR ! ! !

2 305 10 !CMD POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 306 01 !F/O PITCH !+/-16 !DEG ! 29 ! 11 ! 120!BNR ! ! !

2 306 10 !CMD POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 310 01 !L AIL !+/-25 !DEG ! 29 ! 11 ! 60!BNR !AIL ! !

2 310 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 314 01 !L ELEV !+15/-30 !DEG ! 29 ! 11 ! 60!BNR !ELEV ! !

2 314 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 315 01 !STABILIZER!+4/-13.5 !DEG ! 29 ! 11 ! 240!BNR !STAB ! !

2 315 10 !POS 1 !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 330 01 !R AIL !+/-25 !DEG ! 29 ! 11 ! 60!BNR !AIL ! !

2 330 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 334 01 !R ELEV !+15/-30 !DEG ! 29 ! 11! 60!BNR !ELEV ! !

2 334 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 335 01 !STABILIZER!+4/-13.5 !DEG ! 29 ! 11 ! 240!BNR ! ! !

2 335 10 !POS 2 !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 356 01 !MAINT ! ! ! ! ! 60!ISO ! ! !

2 356 10 !ISO 5 ! ! ! ! ! ! ! ! !

-------------------------------------------------------------------------------

| PARAMETER LIST PARAMETER CHARACTERISTICS (NUMERIC) |

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

1 361 01 !L SPLR 1 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR ! ! !

2 361 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 362 01 !L SPLR 2 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR !LSP 2! !

2 362 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 363 01 !L SPLR 3 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR !LSP 3! !

2 363 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 364 01 !L SPLR 4 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR !LSP 4! !

2 364 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 365 01 !L SPLR 5 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR !LSP 5! !

2 365 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 371 01 !R SPLR 1 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR ! ! !

2 371 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 372 01 !R SPLR 2 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR !RSP 2! !

2 372 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 373 01 !R SPLR 3 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR !RSP 3! !

2 373 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 374 01 !R SPLR 4 !+/-50 !DEG ! 29 ! 11 ! 240!BNR !RSP 4! !

2 374 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 375 01 !R SPLR 5 !+0/-50 !DEG ! 29 ! 11 ! 240!BNR !RSP 5! !

2 375 10 !POS !0.09 ! ! ! ! ! ! ! !

! ! ! ! ! ! ! ! ! !

1 377 01 !EQUIPMENT ! ! ! 11 ! ! 240!HEX ! ! !

2 377 10 !IDENTIFIER!06 C ! ! ! ! ! ! ! !

NOTE: A/C NOSE-DOWN <------> PITCH CMD position is negative.
A/C NOSE-RIGHT <-----> YAW CMD position is negative.
A/C R WING DOWN <----> ROLL CMD position is negative.

H. Discrete Outputs

(1) FCDC1

-------------------------------------------------------------------------------

NAME ELECTRICAL LEVEL TO SIGNAL STATUS

-------------------------------------------------------------------------------

CAPT R PRIORITY LT ON GND/O C ANN LT CAPT BOARD GND=ON

CAPT G PRIORITY LT ON GND/O C ANN LT CAPT BOARD GND=ON

FCDC VALID GND/O C FCDC2 GND=VALID

F/O R PRIORITY LT ON GND/O C ANN LT F/O R RLY GND=ON

F/O G PRIORITY LT ON GND/O C ANN LT F/O G RLY GND=ON

(2) FCDC2

-------------------------------------------------------------------------------

NAME ELECTRICAL LEVEL TO SIGNAL STATUS

-------------------------------------------------------------------------------

CAPT R PRIORITY LT ON GND/O C ANN LT CAPT R RLY GND=ON

CAPT G PRIORITY LT ON GND/O C ANN LT CAPT G RLY GND=ON

FCDC VALID GND/O C FCDC1 GND=VALID

F/O R PRIORITY LT ON GND/O C ANN LT F/O R BOARD GND=ON

F/O G PRIORITY LT ON GND/O C ANN LT F/O G BOARD GND=ON

[Rev.10 from 2021] 2026.03.31 23:59:45 UTC